Eric (Rick) Mattern Email & Phone Number

San Diego, CA, US

San Jose, CA, US

Santa Clara, California, US

San Diego, California, US

San Jose, CA, US

Acquired by TDK

Altera acquired by Intel Semi-custom and Full Custom layout of cells and blocks. Explore and Implement new types of automation to streamline the implementation of very strict design rules

Santa Clara, California, US

Place and Route, Semi-custom and Full Custom layout of cells and blocks. CAD support for the group.

San Jose, CA, US

Full Custom layout and P&R of both chips and blocks including floorplanning and timing closure, and CAD support and flow

San Jose, California, US

CAD support and development for all aspects of IC engineering ( front end to back end). Brought up the the NC (RTDA - Network Computer) job scheduler with pre-emption for token based simulation jobs. Managed the job queues, licensing, tool and PDK installs. Full custom layout of high speed RF analog circuits and chips

San Jose, California, US

Full custom layout. Brought up and configured the Cadence semi-custom router and Abstract Generator

Full custom layout of high speed RF analog circuits and chips with Cadence VXL. Lead the layout effort for the 2008 EDN chipset of the year. P&R of digital blocks and chips. On time Tape out of multi-chip reticules on a very aggressive schedule. Built custom libraries and pCells including transistors, pads, and transmission lines for flow and circuit.

Santa Clara, California, US

Astro P&R of digital blocks and chips. Full custom layout of high speed analog circuits and chips with Cadence VXL. Physical verification and CAD development.

Barcelona Design - PDK development and flow developmentCanesta - full custom layout and verification

Full custom layout of high speed RF analog circuits 40Ghz and chips for the Long-Haul optical market with Cadence VXL. On time Tape out of multi-chip reticules on a very aggressive schedule Built custom libraries and pCells including transistors, pads, and transmission lines for flow and circuit enhancement Responsible for all CAD issues for both tools and.

Neubiberg, München, DE

Physical design of full custom analog and P&R of digital circuits, and Pads, and mixed-signal blocks and chips using Cadence ACPD, Virtuoso, Milkyway, Apollo, Silicon Ensemble, and IC Craftsman (ICC), Floorplanning, CTS, and timing closure with Arcadia, StarRC and Vampire. Back-end verification with Dracula and Vampire Perform schematic capture and resolve.

Amsterdam, Noord-Holland, NL

Physical design of large digital blocks from netlist to tapeout using a wide variety of tools including Silicon Perspective, Avanti Apollo, Saturn, StarRCXT and other in-house tools. Responsible for timing closure and resolve antenna issues. Hercules LVS and DRC. Dracula and Hercules runset development. Responsible for designs on Cadence tools and.

Responsible for the.35um StdCell and Custom library front-end design using Composer. Key role in IC integration from multiple platforms, tool migration, upgrades and flow. Perform Chip/library Verification (LVS, SVS) with Dracula. Heavy PCB design. created PCB component library with Concept.

Santa Clara, California, US

Logic Design - functional blocks including state machines, ram interface, combinational logic, and test logic required for the ATPG system at both the chip and PCB level including scan, ram test, and clock muxing. Simulation - Developed the test platform for this project which matched the actual H/W and provided simulation at the block, chip, PCB, and.

Yes, Electronic Technology

Education record