Eric S. Email & Phone Number

Ottawa, On, Ca

Kanata, Ottawa, Canada Area

Responsibilities: * Manage Risk, Schedule, Tasks, Hiring, Lead & Mentor team and Intern * Develop schedules and provide project tracking matrix * Working with architects & customers to develop specifications * Establish Hardware/Software requirement for verification * Evaluate and Select tools for the verification platform * Architect and Implement Verification Platform in System Verilog (UVM), C/C++, SystemC, … * Architect and implement portable test methodology to support Verification, FPGA Validation, SoC * Verification and bring-up * Write test stimulus for functional & code coverage * Write design specifications & DV test plan. * Code UVM assertion-based test-benches to verify the design * Debug complex system-level simulations * Model the design in C/C++, SystemC, … * Emulate the design on FPGA-based systems * Resolve & Validate silicon bring-up design issues

Ottawa, Canada Area

Ottawa, Canada Area

Kanata

All the following system includes Embedded Processor (MicroBlaze, Power PC and DSP), external Processor, DSP, CPLD and system chip (SoC). Software and hardware are closely integrated to provide the best performance.Projects:• Astro-H Metrology System (CAMS): The System measure the displacement of the Hard X-ray Imager relative to the satellite.• IVIGMS: Integrated Vision, Imaging and Geological Mapping Sensor (IVIGMS) is a hybrid vision system targeted rover mounted robotic prospecting and mapping applications.• Angels: A Laser Range Finder that is capable of 20 km with resolution of +/- 2 meters• TriDar: A LiDar camera system including Tri-angulations, Time of Flight (ToF) and infrared camera.• LRVS: Luna Resource Vision System. • LROS: Long-Range Optical Sensor using a CMOS Image Sensor.• LMS: Is a Laser Metrology System.Task:• Establishing Hardware/Software requirement for verification.• Evaluate and Select tools for the verification platform.• Architect and Implement Verification Platform in System Verilog.• Architect and implement the testcase methodology.• Architect and define system specification.• Provide and Establish the Schedule for the Verification• Architect, wrote and design FPGA’s.• Wrote testcases.• Lab Debug and integration.• Used the following tools: Cadence Verification Suite, System Verilog (OVM, UVM), Verilog, C/C++, Python, “Trac” Bug report Software, Microsoft Office Suite

Kanata

The ZORO2400 is a wireless audio device that uses the 2.4 GHz band to provide lossless audio transmission with a robust interference management. This device includes an R8051 microcontroller used to control the custom hardware. Used the following tools: Uv2 (uVision) Suite, C/C++, Seapine “Test tracker” Bug report Software, Wikipedia, Microsoft Office Suite, Cygwin, Microsoft Visuat Studio, TCL, Makefile.• Establishing Hardware/Software requirement for verification• Evaluate and Select tools for the verification platform• Architect and Implement Verification Platform in System C (OVM, UVM) and C/C++• Architect and implement the testcase methodology• Mentor to all the members of the verification team (+/- 6 people)• Provide and Establish the Schedule for the Verification• Member of Signoff and release process• Help RTL writers in the design of their own blocks• Wrote multiple testcases• Used the following tools: Cadence Verification Suite, C/C++, SystemC, Verilog, Seapine “Test tracker” Bug report Software, Microsoft Office Suite

Nepean

Project part of ATI division (Advance Technology Investment), the goal of this project was to make proof of concept of a hardware/software platform that could do Worm signature scan/detection using FPGA/Micro Controller.Q192 is an OC192 (10 Gbits/s) data rate queuing and traffic management Asics. Can support both packet and ATM traffic. • Establishing Hardware requirement for verification• Evaluate and Select tools for the verification platform• Architect and Implement Verification Platform in Vera• Architect and implement the testcase methodology• Mentor to all the members of the verification team (+/- 10 people)• Help RTL writers in the design of their own blocks• Wrote multiple testcasesUsed the following tools: DEBUSSY, VCS , Makefile, Vera, Verilog, C/C++, synchronicity, LSF, UNIX script,

Montreal, Canada Area

Implementation of the ITU G.729AB voice compression algorithm. Using the Conjugate Structure Algebraic Codebook Linear Prediction algorithm, 16-bit samples of speech made at 8 kHz are compressed into an 8kb/s stream.Voice activity detection with comfort noise generation further reduces the average bit rate during silence periods. This is especially useful in packet-based systems such as voice-over-IP. Data is communicated in frame sizes of 10ms. The overall delay of the algorithm is 15ms.Built a Core that can be used in multiple devices according to the UTOPIA Level 1/2 specifications.