Wayne Eric Burk Email & Phone Number

Cupertino, Ca

Santa Clara, Ca

Tegra Camera ASIC/HW Designer Unit lead involving design for high bandwidth, error detection, software synchronization, and low power. Responsible for uarch, rtl coding, formality, synthesis, and netlist checks.Tegra 4 Clocks Lead.Lead team of 10 people involved in chip wide clock architecture. Worked with IP teams to determine their clocking needs and fit into the system. Created flow to show possible clock sources given number of PLLs and IPs neeeds. Implemented local and global high speed clock routing.Was responsible for setting team priorities and load balancing tasks.Worked with DFT and VLSI teams for desired PLLs and DFT functionality needed in next generation Tegra Chip. Tegra 2/Tegra 3 Chip Level LeadI was responsible for creating netlist from synthesis and delivering a quality product to DFT and PNR. I worked with the library group to bring in requested cells and QA timing arcs and properties.I coordinated and ran full chip synthesis across all IP teams. I worked with IP leads on issues and advised on timing and formality fixes. I coordinated and was responsible for netlist checks. I owned the health of the chip tree and worked with cad on custom and industry standard tools to help transitions into the tree. Tegra 1 L2 Cache Design Unit OwnerI designed and implemented an L2 cache to pair with ARM core. I was responsible debug, synthesis, and timing closure.Mobile 3D Texture Unit OwnerI designed and implemented OpenGLES features for texture unit targeted for a low power mobile device.Mobile Video TeamPart of team tasked with implementing H264/WMV9 video decode for a mobile chip. I designed and implemented deblocking functions of standard.Physical Design Team Partition/Top Level OwnerI have owned multiple partitions and worked on timing closure over past mobile chips from pre-Tegra to Tegra 3. Responsible for creating and applying ecos, closing timing, and working with teams across a wide variety of geographies.

Host Bus Interface DesignerWrote uarch and implemented Sun proprietary interface protocol.Followed design all the was from uarch to beta testing. Debugged, synthesized, equivalency checking, bringup, and beta testing with customers.Test Vector LeadLead test vector development for GFX chip working with LSI logic as our foundry. Ran team of 5-10 people to achieve coverage goals and fill gaps found during bringup.

Ms, Electrical Engineering

Bs, Electrical Engineering