Eric Heiden Email and Phone Number

Primary focus in verification of complex FPGA-based systems.Technical experience:-SystemVerilog and UVM based testbench design.-Extensive usage of VHDL as a simulation language using many VHDL 2008 features. -Mentor Modelsim/Questa simulators, python, perl, make, git, GForge.-FPGA Design experience using both VHDL and Verilog - with Xilinx and Altera FPGAs and their respective development tools (ISE, Quartus, synplify).-Analog electronic sensor/transducer development and testing.-Microcontroller application development.Interested in opportunities in the fields of Digital Design and Architecture, especially involving FPGA/ASIC verification and/or design. Also interested in Digital Signal Processing related fields. Interested in systems integration oriented positions as well. Proficient in the German Language.