Eric Jackowski Email & Phone Number

San Diego, Ca, Us

Design Verification of the Hexagon DSP.

Menlo Park, Ca, Us

• DVCON 2022 Paper - ”Flattening the UVM Learning Curve: Automated Solutions for DSP Filter Verification”• Developed Internal ASIP Generation Tool Demo showing off the creation of all the needed custom instructions, ISS, RTL and Verification collateral. • Created Smoke and Sanity regression CI jobs using Meta Internal SW tooling• Attend Cross Functional Meetings to identify opportunities for PPA savings using our internal solution.

Austin, Tx, Us

• Managing a total of nine designers, verifiers and a software engineer.• Identify, hire, mentor and empower top talent.• Responsible for identifying and delivering strategic opportunities to scale and increase efficiency across IoT Design, Verification, and PreSilicon Validation. • Identify and drive initiatives improving IoT efficiency and scalability of license, compute, and storage usage. • Developed the first IoT FPGA Presilicon Validation Compute Farm.• Successfully shifted left SW development and Radio performance signoff by 3 months deploying a continuous delivery strategy for the IoT PreSilicon FPGA platform.• Owned development, maintenance and enhancements of the Radio Subsystem Testbench including UVM, Embedded C code, Python Radio Configurator, SV assertions, and SV Real Number Modeling.• Led the evaluation of Questa Formal along with the development of the policies and methodologies for usage across all IoT for Lint, Formal Lint, CDC, RDC, and Formal property checking.• Architected a scalable verification methodology for Software Defined Radio coprocessors using Formal and UVM to close coverage on interfaces and control logic.• Accelerated the verification of a Software Defined Radio by implementing reusable and scalable tests at the Radio Subsystem level, the SoC level and the FPGA platform.• Reduced Radio Datapath IP verification by one week through the development of a MATLAB in Verification flow for bit accurate matching, automated C DPI interface creation, and automated UVM testbench generation. • Lead the IoT adoption of Cadence vManager for verification planning, regression management, design synthesis and power tracking.• EDA tool vendor management including tracking the closure of tool bugs, driving new tool features, evaluating new tools, and providing tool training to designers and verifiers.

Austin, Tx, Us

• Managed three junior designers developing and verifying Radio IP for all of the IoT Wireless SoCs.• Identify, hire, mentor and empower top digital design talent• Radio verification lead responsible for managing Radio regressions, test plans, models and testbenches.• Developed a Radio Subsystem UVM Testbench containing the digital radio, ARM M0+, RAMs, and RNM RF Model. • Led the SoC cross discipline team responsible for the lowest power BTLE Wireless SoC.• Achieved 10x acceleration of Radio Verification using a SubSystem verification methodology• Transformed 150+ separate SoC level tests into one parameterized test to increase verification efficiency.• Successfully shifted left RF Software resulting in first day silicon Radio bringup success by integrating the Radio Configurator and RF Software into simulation and FPGA PreSilicon Validation.• Developed a verification methodology to achieve bit accurate matching between RTL and MATLAB.• Created fixed point MATLAB models of decimators, sample rate converters, and a cordic.• Guaranteed AHB Compliance of all AHB Masters in the Radio Subsytem by utilizing formal verification.• Mentored team members on ARM M0+ and AHB during the M0+ RF Sequencer subsystem development.• Enhanced debug efficiency through team member training on the AMBA AHB Multi-layer architectures, ARM M0+ architecture, and ARM Subsytem features.• Simplified RF Model Debug and integration by making the model a separate IP for design and verification.• Proactively reduced Radio integration bugs by implementing a structural code check at the integration layer.

Austin, Tx, Us

• SoC Design lead of the EFR32XG13 wireless SoC achieving first silicon success by developing schedules, release candidate milestones, and finalizing the PG checklist with various cross functional teams. • Responsible for the EFR32XG13 architecture updates, design updates, detailed power analysis, verification regression management of all SoC and IP tests, and project issue tracking.• Verification lead of the EFR32XG12 wireless SoC overseeing the regression management for all SoC and IP tests, EDA tooling updates, gate simulations, power vector delivery, and revision control training and tooling.• Developed the ARM Coresight Debug subsystem, ARM M33 subsystem, the ARM M0+ Secure Element subsystem, and the SoC Trustzone Bus Level Security.• Digital Design lead of a Power Isolation chip using analog on top methodology while owning the architecture, design, verification, synthesis and static timing. • Successfully shifted left SW development by developing and executing a FPGA prototype strategy.• Exposed 4x more GPIO by developing a more flexible SoC GPIO pin multiplexing strategy. • A more efficient RNM flow developed by transitioning to the SystemVerilog Real Number Modeling.• Executed mixed signal simulations while developing the digital controller to a high precision analog frontend.

Austin, Texas, Us

Digital logic IP design, verification, and modeling with a focus on advanced modem technologies including Turbo Decoders, Viterbi Decoders and Vector Processors. Synthesize gate level netlists for critical path timing analysis, area analysis and ECOs. Develop firmware and verification tests using C++, Matlab and proprietary assembly. • Designed and verified a scalable Radix-4 parallel turbo decoder capable of meeting the 3GPP HSDPA+ bit rates. Created a constrained random test environment for the turbo decoder input buffer. Incorporated cycle accurate C++ model into top level turbo decoder testbench.• Adapted the viterbi decoder IP bus interface to use AHB. Performed block level and chip level Verification. IP level power simulations performed on RTL and gate level netlist. • Implemented a scalable IEEE-754 vector floating point arithmetic unit and data type converter. Created a constrained random testbench for verification of all possible arithmetic unit instructions and data types. Synthesized each block for critical path timing analysis and area analysis. • Developed a special vector arithmetic unit that calculates arctangent, square root, reciprocal square root and reciprocal using linear interpolation. Verified using Matlab bit exact models and processor instruction set simulator. • Metric driven verification environment used to verify AXI interface block. Generated functional coverage covergroups and assertions for signoff. Analyzed code coverage and functional coverage against coverage goals and verification plan in order to constrain random tests to exercise any missing coverage or points in the verification plan.

Falls Church, Va, Us

Employ FPGAs to interface different communication protocols for military applications. Design RF systems and algorithms for use in Radar Warning Receivers. Develop software application GUIs, DLLs and low level drivers for testing and controlling FPGAs. Received Government Secret Security Clearance.• Enabled early software development by architecting and designing an interface FPGA consisting of two microcontrollers using shared memory and seven communication protocols; Ethernet, Usb,1553, Srio, RS-422, RS-485, RS-232. • New business acquired by designing a proof of concept Radar System along with a corresponding Radar Warning Receiver containing multiple DSP blocks; interpolator, decimator, vector modulator and dual phase offset adder.

Santa Clara, California, Us

Architect, design, synthesize and verify digital logic for production worthy ASICs and IP using Verilog and SystemVerilog. Utilize gate level netlists for logic equivalence checks, timing analysis and sdf back annotated gate simulations. Develop firmware and verification tests using C, C++ and SystemC. Bring up ASICs in the lab for functional tests and chip characterization. • Executed a six month schedule to develop a DisplayPort to VGA and LVDS translator ASIC. Verification effort reduced by quickly acquiring knowledge of SystemVerilog in order to architect and implement a self checking constrained random test environment. Engineered the display controller, DAC controller and I2C controller. • Successfully ECOed an existing display controller chip in production by increasing the memory for larger screen sizes. Verified ECO in RTL using logic equivalence checks and verification tests written in C.• Promptly completed the verification of the memory controller front end for a production Application Processor. The memory controller front end was an AHB to AXI Bridge consisting of ten AHB ports to 4 AXI ports. • Engineered a DVB-H OFDM demodulator SoC with successful integration of the demodulator. Achieved bit for bit comparison between Matlab and RTL in designed blocks; ITB, LPF, DFE, FFT, AGC, 4x4 complex matrix multiplier, ADC control block. Accomplished MBRAI-II performance levels using Palladium hardware accelerator.

Austin, Tx, Us

Created a validation test suite using a Phillips Evaluation Board with an ARM7 CPU. Defined and developed firmware drivers for SSI/SPI, UART, I2C, DAC and SRAM. Validated test boards in the lab using oscilloscopes and logic analyzers. Engineered a testing infrastructure using FreeRTOS. Used the ARM Developer Suite to verify the FPGA SoC hardware model with various tests written in C.

Armonk, New York, Ny, Us

Constructed directed tests in the IBM verification environment for the verification of the Xbox 360 Front Side Bus. Verification Environment expanded as needed using C++. Communicated with designers to resolve bugs and increase code coverage.

M.S., Computer Engineering

B.S., Computer Engineer