Fpga Verification Engineer
Current
Feb 2022 - Present
AeroLeads people directory · profile
Eric Thorne Email & Phone Number
FPGA Verification Engineer
at
Joby Aviation
1 work email found
@ontera.ca
5 phones found area 831, 304, and 408
LinkedIn matched
✓ Verified May 2026
4 data sources
Profile completeness 100%
Current company
Role
FPGA Verification Engineer
Location
Santa Cruz, California, United States
Who is Eric Thorne? Overview
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Quick answer
Eric Thorne is listed as FPGA Verification Engineer at Joby Aviation, based in Santa Cruz, California, United States. AeroLeads shows a work email signal at ontera.ca, phone signal with area code 831, 304, 408, and a matched LinkedIn profile for Eric Thorne.
Eric Thorne previously worked as Principal Electrical Engineer at Ontera and Engineer Guy at Two Pore Guys, Inc.. Eric Thorne holds M.S., Computer Engineering from University Of California, Santa Cruz.
Company email context
Email format at Joby Aviation
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{first}.{last}@ontera.ca
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AeroLeads found 1 current-domain work email signal for Eric Thorne. Compare company email patterns before reaching out.
Profile bio
About Eric Thorne
While at Xilinx, I gained extensive experience in: Data translation automation, Scripting, Electrical Failure Analysis and Isolation, Physical Failure Analysis in relation to FPGA architecture, design and test.While at Two Pore Guys/Ontera I worked with: Transimpedance Amplifiers, Microcontrollers, Rapid Prototyping Board Design/Schematics/Layout, and EMI/EMC certification.Currently at Joby doing: FPGA design verification using System Verilog and UVM
Listed skills include Silicon Interposer, Atpg, Hardware Architecture, Logic Design, and 41 others.
Current workplace
Eric Thorne's current company
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10 roles
Eric Thorne work experience
A career timeline built from the work history available for this profile.
Principal Electrical Engineer
Ontera
Two Pore Guys is now Ontera!Hardware engineer doing digital system architecture, board design and layout. Dabbling in FPGA design and firmware as well.Designed boards for systems in the “NanoDetector” product, including a PCR system for rapid heating and cooling using compressed air and LEDs, with IR sensors for PID feedback. Pneumatic control systems via.
Apr 2019 - Dec 2021
Engineer Guy
Two Pore Guys, Inc.
Hardware Engineer -- Created rapid heating/cooling systems (PCR & LAMP) for a bio-molecular metering system, firmware development, architecture(s) evaluation, analog interface board design & layout.
Feb 2016 - Apr 2019
Senior Staff Engineer
Manage a small group responsible for the automated translation of sort/final test fail die data to defect locations. We also provide scripting services for the larger yield group, can perform electrical failure analysis on specific die, and are working with next generation test chips in a similar capacity. We are also involved in the development and.
Jul 2011 - Jan 2016
Staff Product Engineer
Continuing all responsibilities from previous position, but constantly updating/refreshing them for new products. Took over the automated data translation of sort/final test data. Developed new tests and diagnostic/isolation methodologies for our 3D products.Developed scripts to go from tester fail data to layout location, including automation of layout.
Sep 2006 - Jul 2011
Senior Product Engineer
Responsible for Virtex2Pro's PPC test and diagnostics. Developed BIST engine for Xilinx designed logic around IBM's PP405 core. Fault graded and reported on Xilinx hard IP blocks.Transitioned to the diagnostic methodologies group in the yield organization responsible for the development of back end process specific test patterns for health of line.
Apr 2002 - Sep 2006
Product Engineer
Joined Xilinx in the Speed Files group responsible for the accurate timing of all resources in the device. Worked on a special project for an A&D customer to help them design an in system 100% stuck-fault test methodology plus an in system self readback of Virtex devices (before icap). This work became the basis of Xilinx's EasyPath program.
Mar 2000 - Apr 2002
Intern
3 month summer intern. Application of UCSC's diagnostic tools in an industrial environment
May 1999 - Sep 1999
Intern
3 month summer intern. Helped establish proof of concept, and started initial development of a VLSI fault diagnosis tool
Jun 1998 - Sep 1998
Intern
3 month summer intern. Continued development of Inductive Fault Analysis tool in an industrial environment
Jun 1997 - Sep 1997
2 education records
Eric Thorne education
M.S., Computer Engineering
University Of California, Santa Cruz
B.S., Computer Engineering
University Of California, Santa Cruz
FAQ
Frequently asked questions about Eric Thorne
Quick answers generated from the profile data available on this page.
What company does Eric Thorne work for?
Eric Thorne works for Joby Aviation.
What is Eric Thorne's role at Joby Aviation?
Eric Thorne is listed as FPGA Verification Engineer at Joby Aviation.
What is Eric Thorne's email address?
AeroLeads has found 1 work email signal at @ontera.ca for Eric Thorne at Joby Aviation.
What is Eric Thorne's phone number?
AeroLeads has found 5 phone signal(s) with area code 831, 304, 408 for Eric Thorne at Joby Aviation.
Where is Eric Thorne based?
Eric Thorne is based in Santa Cruz, California, United States while working with Joby Aviation.
What companies has Eric Thorne worked for?
Eric Thorne has worked for Joby Aviation, Ontera, Two Pore Guys, Inc., Xilinx, and Ibm.
How can I contact Eric Thorne?
You can use AeroLeads to view verified contact signals for Eric Thorne at Joby Aviation, including work email, phone, and LinkedIn data when available.
What schools did Eric Thorne attend?
Eric Thorne holds M.S., Computer Engineering from University Of California, Santa Cruz.
What skills is Eric Thorne known for?
Eric Thorne is listed with skills including Silicon Interposer, Atpg, Hardware Architecture, Logic Design, Cadence Virtuoso, Arduino, Test Automation, and Xilinx Vivado.
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