Two Pore Guys is now Ontera!Hardware engineer doing digital system architecture, board design and layout. Dabbling in FPGA design and firmware as well.Designed boards for systems in the “NanoDetector” product, including a PCR system for rapid heating and cooling using compressed air and LEDs, with IR sensors for PID feedback. Pneumatic control systems via microcontroller. Stepper motor driver boards. Resistive heater via LED power supply. PCIe based FPGA system for data aggregation and processing. Responsible for system EMI/EMC certification. Led a team of two responsible for all the electronics in the system.

Hardware Engineer -- Created rapid heating/cooling systems (PCR & LAMP) for a bio-molecular metering system, firmware development, architecture(s) evaluation, analog interface board design & layout.

Manage a small group responsible for the automated translation of sort/final test fail die data to defect locations. We also provide scripting services for the larger yield group, can perform electrical failure analysis on specific die, and are working with next generation test chips in a similar capacity. We are also involved in the development and diagnostics of our 3D products.I also provide test patterns for the monitoring of the specific back end process steps, and diagnostic isolation scripts for those patterns.

Continuing all responsibilities from previous position, but constantly updating/refreshing them for new products. Took over the automated data translation of sort/final test data. Developed new tests and diagnostic/isolation methodologies for our 3D products.Developed scripts to go from tester fail data to layout location, including automation of layout capture isolation location on both monolithic and 3D die.

Responsible for Virtex2Pro's PPC test and diagnostics. Developed BIST engine for Xilinx designed logic around IBM's PP405 core. Fault graded and reported on Xilinx hard IP blocks.Transitioned to the diagnostic methodologies group in the yield organization responsible for the development of back end process specific test patterns for health of line monitoring. Developed diagnostic isolation patterns for the same tests. Performed many die level electrical failure analyses on wafer sort, final test, EFR and LFR failing die.

Joined Xilinx in the Speed Files group responsible for the accurate timing of all resources in the device. Worked on a special project for an A&D customer to help them design an in system 100% stuck-fault test methodology plus an in system self readback of Virtex devices (before icap). This work became the basis of Xilinx's EasyPath program.

3 month summer intern. Application of UCSC's diagnostic tools in an industrial environment

3 month summer intern. Helped establish proof of concept, and started initial development of a VLSI fault diagnosis tool

3 month summer intern. Continued development of Inductive Fault Analysis tool in an industrial environment