System-On-Chip Design Engineer
CurrentRTL design of various generic OTN building blocks.
Nov 2016 - Present
AeroLeads people directory · profile
Erik Andersen Email & Phone Number
ASIC/FPGA design engineer | uArchitect | Design | Implementation | RTL | Verification | Debug | Verilog | VHDL | Team
at
Intel Corporation
LinkedIn matched
✓ Verified May 2026
3 data sources
Profile completeness 86%
Current company
Role
ASIC/FPGA design engineer | uArchitect | Design | Implementation | RTL | Verification | Debug | Verilog | VHDL | Team
Location
Birkerød, Capital Region Of Denmark, Denmark
Company size
Who is Erik Andersen? Overview
A concise factual answer block for searchers comparing this professional profile.
Quick answer
Erik Andersen is listed as ASIC/FPGA design engineer | uArchitect | Design | Implementation | RTL | Verification | Debug | Verilog | VHDL | Team at Intel Corporation, a company with 133841 employees, based in Birkerød, Capital Region Of Denmark, Denmark. AeroLeads shows a matched LinkedIn profile for Erik Andersen.
Erik Andersen previously worked as System-on-Chip Design Engineer at Intel Corporation and FPGA design engineer at Altera. Erik Andersen holds Master'S Degree, Master Of Science Engineering from Dtu - Technical University Of Denmark.
Company email context
Email format at Intel Corporation
This section adds company-level context without repeating Erik Andersen's masked contact details.
Intel Corporation
Review company-level records connected to Erik Andersen before choosing the right outreach path.
Profile bio
About Erik Andersen
Erik Andersen is a ASIC/FPGA design engineer | uArchitect | Design | Implementation | RTL | Verification | Debug | Verilog | VHDL | Team at Intel Corporation.
Current workplace
Erik Andersen's current company
Company context helps verify the profile and gives searchers a useful next step.
Intel Corporation
9 roles
Erik Andersen work experience
A career timeline built from the work history available for this profile.
Fpga Design Engineer
Current
Altera
Apr 2013 - Present
Fpga Design Engineer
Current
Sep 2010 - Present
Principal Design Engineer
RTL design of Ethernet Switching building blocks, mostly traffic management including implementations of WFQ, WERR, WRED, self healing buffer memory architecture, 3-stage hierarchical scheduler.
Apr 2005 - Aug 2010
Senior Staff Design Engineer
Sep 2001 - Apr 2005
Senior Asic Engineer
Dec 2000 - Jul 2001
Asic Engineer
May 1998 - Nov 2000
Research And Development Engineer
Nea-Lindberg A/S
Jun 1991 - Apr 1998
Military Service
Danish Defense Research Establishment
Jan 1990 - Sep 1990
Team & coworkers
Colleagues at Intel Corporation
Other employees you can reach at intel.com. View company contacts for 133841 employees →
JF
Jackie Frazier
Colleague at Intel Corporation
Portland, Oregon, United States, United States
View →
DB
Daniel Braverman
Colleague at Intel Corporation
Israel, Israel
View →
ZG
Zemach Green
Colleague at Intel Corporation
Israel, Israel
View →
DL
Daniil Lyakhov
Colleague at Intel Corporation
Germany, Germany
View →
LS
Laura Spinella
Colleague at Intel Corporation
Pisa, Tuscany, Italy, Italy
View →
KM
Keith Mease
Colleague at Intel Corporation
Gibbstown, New Jersey, United States, United States
View →
张
张聪聪
Colleague at Intel Corporation
Guangzhou, Guangdong, China, China
View →
SC
Siqi Chen
Colleague at Intel Corporation
Austin, Texas, United States, United States
View →
AP
Alma Patricia Perez
Colleague at Intel Corporation
Portland, Oregon Metropolitan Area, United States
View →
BW
Betty Wood
Colleague at Intel Corporation
Folsom, California, United States, United States
View →
Jackie Frazier
Colleague at Intel Corporation
Portland, Oregon, United States, United States
View →
DB
Daniel Braverman
Colleague at Intel Corporation
Israel, Israel
View →
ZG
Zemach Green
Colleague at Intel Corporation
Israel, Israel
View →
DL
Daniil Lyakhov
Colleague at Intel Corporation
Germany, Germany
View →
LS
Laura Spinella
Colleague at Intel Corporation
Pisa, Tuscany, Italy, Italy
View →
KM
Keith Mease
Colleague at Intel Corporation
Gibbstown, New Jersey, United States, United States
View →
张
张聪聪
Colleague at Intel Corporation
Guangzhou, Guangdong, China, China
View →
SC
Siqi Chen
Colleague at Intel Corporation
Austin, Texas, United States, United States
View →
AP
Alma Patricia Perez
Colleague at Intel Corporation
Portland, Oregon Metropolitan Area, United States
View →
BW
Betty Wood
Colleague at Intel Corporation
Folsom, California, United States, United States
View →
1 education record
Erik Andersen education
FAQ
Frequently asked questions about Erik Andersen
Quick answers generated from the profile data available on this page.
What company does Erik Andersen work for?
Erik Andersen works for Intel Corporation.
What is Erik Andersen's role at Intel Corporation?
Erik Andersen is listed as ASIC/FPGA design engineer | uArchitect | Design | Implementation | RTL | Verification | Debug | Verilog | VHDL | Team at Intel Corporation.
Where is Erik Andersen based?
Erik Andersen is based in Birkerød, Capital Region Of Denmark, Denmark while working with Intel Corporation.
What companies has Erik Andersen worked for?
Erik Andersen has worked for Intel Corporation, Altera, Tpack, Broadcom Inc., and Nea-Lindberg A/S.
Who are Erik Andersen's colleagues at Intel Corporation?
Erik Andersen's colleagues at Intel Corporation include Jackie Frazier, Daniel Braverman, Zemach Green, Daniil Lyakhov, and Laura Spinella.
How can I contact Erik Andersen?
You can use AeroLeads to view verified contact signals for Erik Andersen at Intel Corporation, including work email, phone, and LinkedIn data when available.
What schools did Erik Andersen attend?
Erik Andersen holds Master'S Degree, Master Of Science Engineering from Dtu - Technical University Of Denmark.
Find 750M verified contacts
Search by job title, company, industry, location, and seniority. Export verified B2B contact data when you need it.
Start free trialPeople with similar names
Check these profiles if this is not the Erik Andersen you were looking for.
View similar profiles
