Esther Lee

Esther Lee Email and Phone Number

Senior Product Engineer - Analog Technology Development @ Texas Instruments
San Jose, CA, US
Esther Lee's Location
San Jose, California, United States, United States
Esther Lee's Contact Details

Esther Lee personal email

About Esther Lee

Hardworking self-driven electrical engineering who has specialized in system/discrete level product engineering experience as well as mixed-signal IC failure analysis. Expert in supporting new product design from early R&D development to providing product support in manufacturing, reliability/qualification, and sustaining products whilemanaging schedules. Excellent at fault isolation techniques and troubleshooting, strong multitasking, self-managing tasks, and easily adaptable.I am passionate about what I do and believe you must enjoy what you do. It will be a rewarding experience for yourself and your team.Estherlee45@gmail.com

Esther Lee's Current Company Details
Texas Instruments

Texas Instruments

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Senior Product Engineer - Analog Technology Development
San Jose, CA, US
Website:
nvidia.com
Esther Lee Work Experience Details
  • Texas Instruments
    Senior Product Engineer - Analog Technology Development
    Texas Instruments
    San Jose, Ca, Us
  • Nvidia
    Senior Product Engineer
    Nvidia May 2024 - Present
    Santa Clara, Ca, Us
    -Hardware product support with emphasis on power related issues on System, Subsystem and Compute modules in current and upcoming Data Center products
  • Texas Instruments
    Senior Product Engineer - Analog Technology Development
    Texas Instruments May 2022 - May 2024
    Dallas, Tx, Us
    • Perform evaluation, debug, and characterization of integrated circuits to ensure they meet product requirement specifications and manufacturing requirements both at wafer level and package level• Ability to multiplex between projects and maintain project schedules with various process and intrinsic technology teams to develop and qualify new IP process technologies• Work closely with global manufacturing facilities to address product quality, yield management. Scope of work include product spins and derivatives• Support/drive schedules for look ahead qualification prior to internal NPI release• Work with failure analysis team to determine root cause of intrinsic reliability and qualification failures• Manage and drive schedules with IP designers in order to meet PG dates successfully while keeping current to PDK changes
  • Maxim Integrated
    Senior Failure Analysis Engineer - Qa
    Maxim Integrated Mar 2017 - Apr 2022
    San Jose, Ca, Us
    - Determine root cause of IC discrete failures supporting internal NPI products with various business units working in parallel with reliability, design, and R&D groups- Developed fundamental knowledge of failure mechanisms with the use of curve tracer, extensive bench test characterization, utilizing emission/ obirch/ thermal/ analysis at wafer level package, etc.- Fault isolate through destructive analysis in-house support; parallel lap, FIB cross sectioning, and SEM- Proficient addressing fault failure location site through the use of cadence layouts and schematics and determining root cause failure- Issue corrective actions when applicable and good oral/written skills to generate professional failure analysis reports to internal BU teams and Quality
  • International Rectifier An Infineon Technologies Company
    Staff Product Design Engineer - R&D Hi-Reliability
    International Rectifier An Infineon Technologies Company Sep 2007 - Jun 2016
    Neubiberg, München, De
    Staff Product Design Engineer 08/14 - 06/16Sr. Product Design Engineer 08/011- 08/14Product Design Engineer 09/07 - 08/11 • First engineer to successfully complete forward DC/DC resonant switch mode power supply hybrid converter family series: 150Vin-250Vin 20W Single/Dual ranging from -35C to +185C•Pioneer key contributor establishing new BU platform in R&D High Temperature Products •Created/ managed R&D high temperature library which reports improvement activities and all performance reliability analysis between +185C to +225C• Researched & performed HT component reliability stress tests beyond operating conditions while managing equipment/material to support it, i.e. discretes, passives, adhesives, and epoxies• Lead and organized R&D high temperature weekly meetings with design, process, and component engineering teams. Mentored, shared knowledge, and actively performed analysis• Successfully developed initial HT test fixture and bench test setup for die qualification for new product development +200C for >1000 hours• Perform extensive isolated electrical performance characterization at +185C to resolve Burn-in failures; power FETs, rectifiers, & power magnetics• Solid system level understanding of SMPS forward converters/ power stage circuits• Executes first turn on validation test and make modifications when applicable• Generate and present design reviews analyzing product performance/ ppk analysis, stress & thermal analysis, datasheet validation, and qualification report• Owns & drives new product which includes all pertaining documents and modification to derivative designs / i.e. Schematic, BOM, assembly layout, lot travelers, and ECO’s• Manage and support qualification & sustaining products as well as performing engineering reliability tests to ensure success• Responsible engineer for driving multiple hybrid DC/DC high temperature products through early product design phase through completion of qualification
  • Maxim Integrated
    Failure Analysis Engineer - Qa
    Maxim Integrated Mar 2006 - Sep 2007
    San Jose, Ca, Us

Esther Lee Skills

Failure Analysis Semiconductors Testing R&d Analysis Simulations Analog Circuit Design Electronics Cmos Engineering Troubleshooting Engineering Management High Temperature Mixed Signal Analog Debugging Cross Functional Team Leadership Integrated Circuits Ic Silicon

Esther Lee Education Details

  • Uc San Diego Jacobs School Of Engineering
    Uc San Diego Jacobs School Of Engineering
    Electrical And Electronics Engineering

Frequently Asked Questions about Esther Lee

What company does Esther Lee work for?

Esther Lee works for Texas Instruments

What is Esther Lee's role at the current company?

Esther Lee's current role is Senior Product Engineer - Analog Technology Development.

What is Esther Lee's email address?

Esther Lee's email address is es****@****ail.com

What schools did Esther Lee attend?

Esther Lee attended Uc San Diego Jacobs School Of Engineering.

What skills is Esther Lee known for?

Esther Lee has skills like Failure Analysis, Semiconductors, Testing, R&d, Analysis, Simulations, Analog Circuit Design, Electronics, Cmos, Engineering, Troubleshooting, Engineering Management.

Who are Esther Lee's colleagues?

Esther Lee's colleagues are Dennis Sessanna, Kartik Shrivastava, Tarun Singh, Andrea (Andi) Mcpadden, Li Xu, Trisha Saar, Sudhanshu Ranjan.

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