Ethan L. Email & Phone Number

San Diego, CA, US

Bethesda, MD, US

Advocate for device/component traceability throughout the electronics supply chainStudy potential of ECID, PUF, mapping, and other technologies for enhancing SECURITY & TRUST in the semiconductor supply chainSupport designers and subcontractors with EEE component selection for use on a high reliability program

Eindhoven, Noord-Brabant, NL

Test & product engineering for mixed signal IC's.Collaboration with design, bench test, quality, marketing engineers, and vendors for New Product Introductions (NPI). - Hardware and software development (with Advantest 93k test platform). - Work with design team to ensure DFT (design for test) is implemented and cost effective. - Debug IC design and test.

Norwegian PhD Network on Nanotechnology for Microsystems

Oslo, Oslo, NO

Compound Semiconductors - Ceramics - Oxides - Thin FilmsNanostructuring SiGeTransparent oxide transistors with ZnO channelsLi diffusion in thin films of MOCVD grown ZnOInvesitgated the oxidation induced formation of heterostructures in epitaxial SiGe on Si substrates.- Constructed empiric models to describe the redistribution of Ge during oxidation.- X-Ray.

Dallas, TX, US

Technology – 180nm Radio Frequency (RF) / Low Power Wireless System On Chip (SoC) designsDevelopment and execution of test strategy for new product introductions.- Write code for production and characterization test programs.- Design and order final test load board, HTOL test (aka lifetime reliability test) board, and wafer test probe card..

Eindhoven, Noord-Brabant, NL

Technology – 65nm, 90nm, & 120nm Digital SoC’s – 300mm fabNXP fab interface team at ST-Freescale-NXP collaboration fab in Crolles, France.- Provide test support to NXP business groups for new product introductions and first silicon debugs.- Yield enhancement for NXP products produced in the ST-Freescale-NXP collaboration fab.- Development and execution of.

Portland, OR, US

Technology - 120nm & 180nm Application Specific Integrated Circuits (ASICs)Conducted research in testing of digital integrated circuits in the IC Design and Test Laboratory at Portland State University in cooperation with LSI Logic.- Digital IC test research focusing on temperature sensitive defects, minimum voltage (minVDD or VDDmin) and maximum frequency.

San Jose, CA, US

Technology - 120nm & 180nm ASIC’s – 200mm fabProduction line yield enhancement.- Daily monitoring of wafer level product and scribe line parametric test data.- Data and failure analysis to determine root causes for maverick and low yield product.- Individual and team work to identify and rectify systematic yield issues including process marginalities.

Icheon, Gyeonggi-do, KR

Technology - 220nm Synchronous DRAM – 200mm fabManagement of Electrical Parametic Measurement (EPM) section. (aka Process Control Monitor (PCM) or scribe line test section)- Code management for Keithley based EPM test programs.- Integration of new products and technology generations for EPM department.- Production line yield enhancement- Gather, prepare.

Phd, Materials Physics

Msc, Ee

Bs, Physics

Physics & History