Ethan L. Email & Phone Number

San Diego, Ca, Us

Bethesda, Md, Us

Advocate for device/component traceability throughout the electronics supply chainStudy potential of ECID, PUF, mapping, and other technologies for enhancing SECURITY & TRUST in the semiconductor supply chainSupport designers and subcontractors with EEE component selection for use on a high reliability program

Eindhoven, Noord-Brabant, Nl

Test & product engineering for mixed signal IC's.Collaboration with design, bench test, quality, marketing engineers, and vendors for New Product Introductions (NPI). - Hardware and software development (with Advantest 93k test platform). - Work with design team to ensure DFT (design for test) is implemented and cost effective. - Debug IC design and test from first silicon to production. - Cost reduction through test time reduction, hardware design, DFT, and data analysis.Support and train colleagues to improve the expertise, competence, and success of my team.

Norwegian PhD Network on Nanotechnology for Microsystems

Oslo, Oslo, No

Compound Semiconductors - Ceramics - Oxides - Thin FilmsNanostructuring SiGeTransparent oxide transistors with ZnO channelsLi diffusion in thin films of MOCVD grown ZnOInvesitgated the oxidation induced formation of heterostructures in epitaxial SiGe on Si substrates.- Constructed empiric models to describe the redistribution of Ge during oxidation.- X-Ray diffraction (XRD) - characterization of the Ge content and layer thicknesses in SiGe heterostructures.- Variable Angle Spectroscopic Ellipsometry (VASE) - characterization of layer thicknesses and estimation of Ge content in SiGe heterostructures.- X-ray photo-electron Spectroscopy (XPS) - Evaluation of XPS data to determine elemental composition and chemical state of thermal oxides on SiGe.- Rutherford Backscattering (RBS) - Evaluation of RBS data to determine the elemental distribution in oxidized SiGe.ZnO Thin Film Transistors- Designed, fabricated, and characterized Transparent Thin Film Transistors (T-TFT) with both MOCVD and RF sputtered ZnO channels.- Architectures used include top and bottom gate structures, rectangular and Corbino designs.- Thermal SiO2 and ALD grown Al2O3 used for gate dielectrics.- Various methods used for construction of ZnO transistors and SiGe nanostructures include Electron Beam Lithography, Photolithography, Shadow Mask lithography, Thermal Evaporation, E-beam metal deposition, and Wet Etching.- LABVIEW programs written to control various IV meters for electrical characterization of ZnO transistors.Li diffusion in ZnO- Investigated diffusion of Li in thin films of MOCVD grown ZnO on C and R-plane sapphire substrates using modeling and Secondary Mass Ion Spectroscopy (SIMS) data.- Quartz tubing and sapphire substrates were evaluated as sources of Li contamination.MATLAB used to simulate/model diffusion profiles (Cd in ZnCdO, Li in ZnO, and Ge in SiGe) and to analyze ellipsometry data from oxidized SiGe heterostructures.

Dallas, Tx, Us

Technology – 180nm Radio Frequency (RF) / Low Power Wireless System On Chip (SoC) designsDevelopment and execution of test strategy for new product introductions.- Write code for production and characterization test programs.- Design and order final test load board, HTOL test (aka lifetime reliability test) board, and wafer test probe card.- Characterization, debug, reliability, qualification, lifetime testing, and release to market of TI's CC2530 low power wireless transceiver.- Planning and logistics for assembly, test, and qualification.- Test cost reduction while maximizing reliability and quality.- Very Low Cost Tester (VLCT) - TI proprietary ATEEncouraged use of NVM to store data generated during production test such that the IC testing adds value to the product. Examples are individual die-id, calibration of temperature sensor, and an IEEE address.Worked with design and foundry test engineers to implement unique die-id's for the first time in TI's low power wireless products.Test and characterization work to debug transient failures in embedded SRAM IP block - Use of Very Low Voltage (VLV) testing to minimize cold (-40C) and hot (125C) test stages while ensuring high quality standards.

Eindhoven, Noord-Brabant, Nl

Technology – 65nm, 90nm, & 120nm Digital SoC’s – 300mm fabNXP fab interface team at ST-Freescale-NXP collaboration fab in Crolles, France.- Provide test support to NXP business groups for new product introductions and first silicon debugs.- Yield enhancement for NXP products produced in the ST-Freescale-NXP collaboration fab.- Development and execution of test strategy for new product introductions.- Manage test data feedback between foundry and design groups for IP debug and fab yield enhancement.- Production test implementation of datalogging for SCAN based (e.g. stuck-at) tests to be used for failure diagnosis.- Efficient MBIST based mapping of embedded SRAMs for production test programs.- Digital logic and memory performance characterizations across process corners (Frequency, Voltage, Temperature).- Extremely low voltage testing for defect detection in digital and memory blocks.- Probe card design/order for small pitch 65nm SOC design.- Studied variation in Zero Temperature Coefficient (ZTC) voltage in Fast, Nominal, and Slow process corners.- Verigy ATE testers and Electroglas probers.

Portland, Or, Us

Technology - 120nm & 180nm Application Specific Integrated Circuits (ASICs)Conducted research in testing of digital integrated circuits in the IC Design and Test Laboratory at Portland State University in cooperation with LSI Logic.- Digital IC test research focusing on temperature sensitive defects, minimum voltage (minVDD or VDDmin) and maximum frequency (Fmax) testing, statistical post processing, statistical outlier screening, and spatial yield analysis.- Studied influence of Zero Temperature Coefficient (ZTC) on digital IC performance and proposed novel test methodologies based on this effect. (ZTC aka reverse temperature dependence, temperature variation insensitive, inverted temperature dependence (ITD), and positive or negative temperature dependence)- Frequency, Voltage, and Temperature characterization of LBIST, stuck-at, and Iddq tests.- Credence ATE testers and Electroglas probers.

San Jose, Ca, Us

Technology - 120nm & 180nm ASIC’s – 200mm fabProduction line yield enhancement.- Daily monitoring of wafer level product and scribe line parametric test data.- Data and failure analysis to determine root causes for maverick and low yield product.- Individual and team work to identify and rectify systematic yield issues including process marginalities, process equipment malfunctions, test and design related yield loss.

Icheon, Gyeonggi-Do, Kr

Technology - 220nm Synchronous DRAM – 200mm fabManagement of Electrical Parametic Measurement (EPM) section. (aka Process Control Monitor (PCM) or scribe line test section)- Code management for Keithley based EPM test programs.- Integration of new products and technology generations for EPM department.- Production line yield enhancement- Gather, prepare, and analyze test and production history data.- Physical and electrical failure analysis of non-compliant product.I was employed by Hyundai Semiconductor America (prior to it being renamed Hynix.)

Phd, Materials Physics

Msc, Ee

Bs, Physics

Physics & History