Roberto Herrera Email & Phone Number

Heredia, Costa Rica

Heredia, Costa Rica

Working on Application-specific integrated circuit (ASIC) design for implantable devices for Boston Scientific's Cardiac Rhythm Management (CRM) and Neuromodularion (NM) divisions. Focusing on RTL Verification using System Verilog/UVM methodology.

Heredia, Costa Rica

Verification of embedded firmware for the both the Remote Control and IPG of Deep Brain Stimulation (DBS) and Spinal Cord Stimulation (SCS) Implantable Pulse Generators.Worked in development of the verification environment and libraries for the next generation implantable devices, using Python as the main programming language, and adopting CI/CD development principles. Additionally, developed the first Python scripts to test basic functionality for the next generation implantable generation, using the new infrastructure and environment developed by the team.Moreover, collaborated on developing and debugging Python scripts for firmware verification for the next generation radio frequency generator for pain management ablation treatments.

Global Park

Firmware verification for the Remote Control of Deep Brain Stimulation (DBS) Implantable Pulse Generators.As part of this role, led the RC verification team on developing strategies to write new PHP scripts for firmware verification for new product features, transform the firmware validation tests to migrate from radiofrequency communication protocols to Bluetooth and improve the performance and stability of the verification test suite, while keeping the work on time to deliver verification formals activities and documentation to stay in schedule required to meet the deadlines for comply with FDA applications.

Costa Rica

Managed a team of 10 engineers that developed analog content for: power, thermal, and voltage regulators, spanning from Pre-Silicon validation, to Post-Silicon debug up to high volume production ramp of microprocessors. I led the transition of the team from the server segment into the chipset segment, working in a multi-geo organization (US, Israel, Ireland, Malaysia and Costa Rica) to deliver 2 products to market, and later developing 2 new chipset products. The team followed the Agile/scrum methodology using Rally software and focused on continuous improvement processes, saving ~60hrs/week during 2017 through waste elimination efforts.

Belen, Heredia Costa Rica

Responsible for the analog content simulation and emulation on Pre-Silicon models, test patterns generation, yield improvement and silicon debug on tester for the Fully integrated voltage regulator (FIVR) of a 24-core, 14nm Xeon server product. After several challenges on yield improvement that required enhancements in the content and testing flow, and debugging efforts with the platform teams in Guadalajara, it was possible to intercept the manufacturing readiness milestone to successfully launch the product to market on Q2’2016.

Belen, Heredia, Costa Rica / Austin, Tx

On 2013, relocated to Austin, TX for 8 months to work on the ATPG (scan) content for a 22nm SoC product. On Pre-Silicon, was responsible for pattern generation using Mentor Graphics software for several IPs, as well as the validation on synthesized models. On Post-Silicon, collaborated with performing diagnosis of failing patterns to regenerate improved content. On 2014, was responsible for full chip emulation of ATPG content on a 14nm Server product. As the process was manual and repetitive, worked on scripts generation to automate the emulation runs. reducing execution time from hours to minutes, while eliminating manual errors.

Belen, Heredia, Costa Rica

On 2011, relocated to Austin, TX for 3 months to engage with the SoC DFx team on the Scan Pre-Silicon validation on a 22nm Atom project. During this time, wrote more than 60 System Verilog tests and found/validated more than 80 RTL bugs. I also co-developed a test environment infrastructure, using a Saola/OVM Agent to drive the scan data to the DUT, and a reusable modular test interface. On subsequent SoC projects, wrote additional tests and provided consultation to Post-Silicon teams. From 2012 to 2013, I also acted the team lead for local DFx team, managing a team of 3 people.

Belen, Heredia, Costa Rica

Developed functional test content using IA-32 assembly language or Perl wrappers to screen out defects for the physical layer of Quick Path Interconnect Link on a Xeon Product, achieving a goal of 80% toggle coverage, and for the Gen6 Intel Graphics engine of the Sandy Bridge Processor, both in the Blitter Engine, as well as in the H.264 codec engine.

Belen, Heredia, Costa Rica

Used CAD tools for schematics improvement, static timing analysis, and power/noise optimization for several blocks of Intel’s 1st 45nm Core Processor. I also improved data paths to meet timing requirements and did simulations to verify compliance with voltage requirements on RAM cells.

Belen, Heredia, Costa Rica

Responsible for statistical data analysis and indicators monitoring for maintaining infant mortality and DPM goals on 90nm server products. I also collaborated with data collection and running experiments for a new methodology to screen out units with potential thermal marginality.

Bachelor Of Applied Science (B.A.Sc.), Electrical And Electronics Engineering

Honor Graduate

High School Diploma, High School