Eudes Prado Lopes, Ph.D. Email & Phone Number
@ieee.org
1 phone found area 650
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Who is Eudes Prado Lopes, Ph.D.? Overview
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Eudes Prado Lopes, Ph.D. is listed as CTO at Siloxit, based in San Diego, California, United States. AeroLeads shows a work email signal at ieee.org, phone signal with area code 650, and a matched LinkedIn profile for Eudes Prado Lopes, Ph.D..
Eudes Prado Lopes, Ph.D. previously worked as Chief Technology Officer at Siloxit and Business Development & SoC at Siloxit. Eudes Prado Lopes, Ph.D. holds Ph.D., Computer Science - (Eda) from Pierre And Marie Curie University.
Email format at Siloxit
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AeroLeads found 1 current-domain work email signal for Eudes Prado Lopes, Ph.D.. Compare company email patterns before reaching out.
About Eudes Prado Lopes, Ph.D.
Eudes Prado Lopes managed the Design Service Center in SP, Brazil since its inception in 2014 through 2016. Eudes teamed up with the Optical Communication group to build an ecosystem of ASIC Design whose goal is to implement Optical comm. IP on silicon. Recently, Eudes became Business Manager of CPqD´s Design Service Center.Eudes has 17+ yrs. experience on semi industry worked for large IDMs (Philips and NXP in the Bay Area), as well as for R&D organizations (IMEC-Belgium, CPqD-Brazil). He holds an M.Sc. in EE (COPPE/UFRJ) and a Ph.D. in CS (UPMC-France).Professional Experience: • Design Service Center founder&manager overseeing 40+ designers working from high-level synthesis to GDS2. Manage engagement with customers, partners and providers.• ASIC design project leader on DSM (TSMC 16nm) ASIC block of a DSP for optical comm. application. DSP circuit complexity: 160M+ transistors. Budget: US$25M in 3 yrs.• Physical Design Leader of a full chip ASIC OTN processor TSMC40nm). Chip complexity: 100M+ transistors, Budget US$14M in 3 yrs.• EDA tools procurement.• Program management of DSM ASIC Physical Design activities for European start-ups and internal designs (IMEC).(UMC180,TSMC40 and other).• Trainer on Physical Design Flow and DfM training classes (EUROPRACTICE);• Management of SOC Design Methodology proposal, development and deployment across multiple teams. Methodology Definition for ASIC Flows Implemented throughout Global Distributed Workforce for Digital Video Platform SoC designs. Paper presented:to Philips World-Wide Technology Conference - Paris, November–2005.• Leadership role and Fab/Physical Design Team contact for DfM in Philips/NXP’s ASIC design Center for DCF&Physical Verification.• Risk Management and FMEA for SoC.• Quality Assurance (ISO9001-2000 CMM) • Project lead: BDD-based Design Tool for FPGA Circuits, Placement/Routing/Power Consumption.• ASIC and FPGA synthesis and Place &Route tools developer.• EDA algorithms specialist.
Listed skills include Soc, Asic, Integrated Circuit Design, Ic, and 43 others.
Eudes Prado Lopes, Ph.D.'s current company
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Eudes Prado Lopes, Ph.D. work experience
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Business Development & Soc
Ceo President Of Loentropy Technologies
SOC Design Services Consultant
Manager, Microelectronics Design Services Center - Gcci
Manage Design Services BusinessManage 40+ SoC designers Supervise Multi-million gates projects (40nm and 16nm)Negotiate contracts, finance and EDA tools procurementDesign services and IP business promotionMentor chip design professionals
Business Development Manager
Business Development Manager for the ASIC Design Service Center of CPqD Worldwide customer´s base prospection and relationship New business creation and client retention Bidding process support and follow-up Business strategy planning and forecasting Procurement support and relationship (EDA, Design Services, and Fabs) Design team coaching
Senior Design Engineer
Design Methodology lead of SoC designsQuality leaderFab liaison and Design Verification and Chipfinishing Leader
Sr. Software Engineer
Sr Software Engineer
Eudes Prado Lopes, Ph.D. education
Ph.D., Computer Science - (Eda)
M.Sc., Eletronic Design Automation
Electronics Engineer, Electronics
M.Sc., Electrical And Electronics Engineering
Frequently asked questions about Eudes Prado Lopes, Ph.D.
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What company does Eudes Prado Lopes, Ph.D. work for?
Eudes Prado Lopes, Ph.D. works for Siloxit.
What is Eudes Prado Lopes, Ph.D.'s role at Siloxit?
Eudes Prado Lopes, Ph.D. is listed as CTO at Siloxit.
What is Eudes Prado Lopes, Ph.D.'s email address?
AeroLeads has found 1 work email signal at @ieee.org for Eudes Prado Lopes, Ph.D. at Siloxit.
What is Eudes Prado Lopes, Ph.D.'s phone number?
AeroLeads has found 1 phone signal(s) with area code 650 for Eudes Prado Lopes, Ph.D. at Siloxit.
Where is Eudes Prado Lopes, Ph.D. based?
Eudes Prado Lopes, Ph.D. is based in San Diego, California, United States while working with Siloxit.
What companies has Eudes Prado Lopes, Ph.D. worked for?
Eudes Prado Lopes, Ph.D. has worked for Siloxit, Loentropy Technologies, Cpqd, Imec, and Nxp Semiconductors (Founded By Philips).
How can I contact Eudes Prado Lopes, Ph.D.?
You can use AeroLeads to view verified contact signals for Eudes Prado Lopes, Ph.D. at Siloxit, including work email, phone, and LinkedIn data when available.
What schools did Eudes Prado Lopes, Ph.D. attend?
Eudes Prado Lopes, Ph.D. holds Ph.D., Computer Science - (Eda) from Pierre And Marie Curie University.
What skills is Eudes Prado Lopes, Ph.D. known for?
Eudes Prado Lopes, Ph.D. is listed with skills including Soc, Asic, Integrated Circuit Design, Ic, Semiconductors, Physical Design, Microelectronics, and Eda.
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