Company name change due to a completed acquisition of OCZ Storage Solutions by Toshiba (TAEC). Comprehensive, in System Validation and Characterization of Enterprise SATA SSD and PCIe/NVMe SSD products. Hardware Lab and Hardware R&D Engineering Team Management. • Defined and instituted Enterprise and Consumer level Storage SSD Test Methodology. Contributed in defining SSD Hardware PCB Design Methodology. Worked closely with RDT and Reliability teams to establish adequate sample size for various tests. • Drove the process of resource allocation and sizing required test engineering effort for all Engineering Activities, as well as Failure Analysis and schedule deliveries. Performed engineering analysis, document and communicate Corrective Action Plans (CAPA) for implementation at manufacturing site(s) to avoid low build yield.• Lead execution of all SSD product EVT requirements to delivery and ensure test coverage in accordance with established Marketing Requirement documents (PDRD) and Design Specifications. Performed and debug issues identified during testing to achieve PCISIG and SATA Certification on all SSD products. • Developed trust, working relationships at the team, project stakeholders, senior management, and executive levels. Arranged and facilitate regular interaction with Firmware, Hardware Design, ASIC Design, FAE, and RDT teams. Solicit feedback from various input sources on area for improvement and implement processes to that effect. Established close relationships with equipment vendors for joining business opportunities. • Predicted, identified, and resolved resource and equipment conflicts. Identified problematic areas of design to concentrate the most in testing and provide solutions to Hardware design teams. Document and monitor program risks.• Documented and communicated status, issues and risks to project stakeholders and senior management. Provided Hardware Testing Road-maps to executive management.

In System Validation and Characterization of Enterprise SATA SSD and PCIe/NVMe SSD product. Lab and Engineering Team Management. Established Test Methodology and process of identifying key areas in design to be tested first. Directed initial characterization/validation of critical components to be used in design to identify problem early and communicate back to H/W Design team before Production Boards are in Fab.

• Introduced and implemented “State of the Art” characterization process. Established processes for overall FPGA, Silicon, and Generic SerDes characterization. Setup guidelines for debugging and tuning to meet Industry Standard Interface Specification requirements for silicon and FPGA designs. • Drove the process of project allocation and sizing required engineering effort and establishment of delivery schedules. Combine all interdependencies into a single optimized schedule and plan for the program.• Led execution of all programs from requirements to delivery ensuring on time delivery, in accordance with established SOW, and business objectives. Manage a Portfolio of all High Speed Serial Interconnect compliance and silicon validation/characterization testing activities (i.e. SATA, SAS, USB2, USB3, PCI Express, DP, HDMI, DDR1/2/3/4, and Thunderbolt technologies).• Developed trusted, working relationships at the team and senior management levels. Arrange and facilitate regular interaction with customer teams, including test results and management reviews. Solicit feedback from customers on area for improvement and implement processes to that effect. Establish close relationships with equipment vendors for joining business opportunities. Create MOIs for established High Speed Serial technologies, as well as upcoming technologies to be supported at GRL. Developed opportunities for business continuity when appropriate.• Predicted, identified, and resolved resource and equipment conflicts. Document and monitor program risks.• Documented and communicated status, issues and risks to stakeholders and senior management. Make presentations and escalade critical issues to executive management when necessary.• Drove business objectives to make the right strategic trade-offs for the program

Member of PCISIG-SEG Committee technical staff. Performed PCISIG Compliance tests on vendor’s products for PCISIG Compliance and Certification program (Integrators List) at PCISIG Workshops using Agilent, Tektronix and LeCroy test equipment.

• Hands-on manager and technical lead for seven different PCI/PCI-X and PCI Express I/O Accelerator silicon releases.• Assigned to lead a new program and manage engineering teams in new development of PCI and PCI Express designs to Generic local Bus. • Lead cross-functional execution of the program from requirements to delivery and ensure that a program delivers in accordance with established technical and business objectives. Integrate cross-functional project plans into a single Master Schedule and plan for the program. • Worked with back-end vendors and foundry, to line up resources and define new IP requirements. Conducted Quarterly Engineering Program progress and Risk Analysis to PLX Executive Staff for review and planning. • Align customer expectation with company’s business objective with timely delivery of MCM integration device as a drop-in replacement for legacy devices. • Created Verification, FPGA based Emulation, and Validation Plans. Conducted System bring ups and debug of PCI Express Switches. Evaluated and performed full characterization of PCI Express Gen1/Gen2 SerDes on final products. Generated synthesis scripts and performed full chip synthesis and timing closure during Back-End engineering activities.• Appointed to lead hardware and software engineering teams in emulation of new generation PCI Express Switch and Bridge devices using FPGA-based Emulation Platforms. • Established partnership programs with key PCI Express leaders (Intel, HP, Catalyst). Set the ground work for Validation to reuse most of the Emulation-developed Software. • Led engineers to successfully completed Emulation on time, with critical issues identified before tapeout. Took an initiative to establish an Engineering Department Methodology with Responsibilities, Deliverables, and Milestones set for each sub-department within Engineering. • Successfully deployed newly established methodology within the Engineering Department at PLX.

• Worked as a senior camera technician• Managed sale floor and repair shop. • Responsible for training of new employees