Eugenio Scarpa Email & Phone Number

Torino

Project Manager in charge of supporting the Program Manager for developing the Space Segment for Argotec HAWK for Earth Observation constellation in the framework of the ESA IRIDE program.Technical supervision and consultancy service in support to the Space Segment Development Team.

Torino, Italia

Project Management activities for the ESA AO/1-10240 "Hardening techniques for commercial-off-the-shelf FPGA for digital telecommunication payloads” programme (codename EUFRATE).Overseeing and coordinating a multi-partners consortium in electronics, digital design, and radiation test engineering activities. Activity scheduling, risk and cost management, engineering troubleshooting.

Torino, Piemonte, Italia

Team leader for digital and FPGA design activities in the Electronics Unit.

Torino, Italia

Purposes: - Hardware development on FPGA for space applications;Tasks:- Module specification, simulation, integration and verification based on VHDL and Verilog languages;- Synthesis and implementation on MicroSemi RTG4 and ProAsic3L, Xilinx Virtex-6, Zynq-7000, Kintex-7 devices;- Test procedures; - Technical documentation drafting;Knowledges:- SpaceWire, ECSS and CCSDS specifications;- ARM AMBA AHB2, AHB-3 Lite, APB3, APB4, AXI-4, AXI4-Stream;- SDRAM, DDR2, DDR3 SDRAM memories;- ONFI-compliant NAND-based Flash memories controller with Bad-block management and DMA transfer in VHDL;- SEE reliability based on FIT (Failure In Time) estimation data analysis;- UART, SPI, I2C, CAN serial protocols;- ArgoMoon Electrical Propulsion System (EPS) FPGA architecture, including PWMs, ADCs and LCLs, anti-SEU/SET;- MicroSemi Libero SoC;- Synopsys Symplify Pro;- MentorGraphics ModelSim ME Pro/SE;- Xilinx Vivado HLx;- Synthesis optimization techniques, STA, FP, power consumption analysis, PAR, clock domains crossing, register retiming, clock buffering techniques for FPGA development;- Argomoon On-board Computer (OBC) architecture interface with Cobham Gaiser GR712RC CPU and MicroSemi RTG4 FPGA development;- Cobham Gaisler LEON3 softcore VHDL development on Xilinx Virtex-6;- CCSDS CUC and Time Manager CTM equivalent VHDL synthesizable cores development;- NI LabView and LabView FPGA for testing and integration;- CCSDS Standards for Data Packaging;- Image compression algorithms;- AES128 encryption algorithms;- MATLAB/C programming;- TCL scripting.

Torino

Inserito nell'organico della Commissione Arbitri Nazionale di Serie A-B per la stagione sportiva 2024/25.

Torino, Italia

Inserito nell'organico della Commissione Arbitri Nazionale di Serie C per le stagioni sportive 2019/20, 2020/21, 2021/22, 2022/23 e 2023/24.Inserito nell'organico della Commissione Arbitri Nazionale di Serie D per le stagioni sportive 2016/17, 2017/18 e 2018/19.Inserito nell'organico della Commissione Arbitri Interregionale per le stagioni sportive 2012/13 e 2015/16.

Torino, Italia

Purposes:- Hardware development on FPGA for electronic measurements on railways security;Tasks:- VHDL-based digital logic design, hardware description and simulation within the Xilinx ISE Design Suite and Xilinx Vivado Suite tools;- manufacturing, assembling and instruments testing;- technical documentation drafting;- customer assistance.Knowledges:- Digital design and custom logic (HDL) development along with pertaining knowledge of the workflow phases of specification, simulation, debug, synthesis, optimization, implementation, constraint specification, mapping, PAR, static timing analysis (STA);- design development on Xilinx Zynq-7000 SoC and Xilinx Spartan-6;- development of custom logic for synchronization between heterogeneous electronic instruments and FIR filtering;- professional application within the Xilinx ISE Design Suite and Xilinx Vivado Suite tools;- standard application within the Altera Quartus-II and ModelTech ModelSim tool;- C language-based verification models, test patterns generation and interface driver development;- knowledge of the AMBA AXI-4, SPI, Ethernet and UART communication protocols;- learning of utilization of electronic measurement instruments (function generators, power supplies, oscilloscopes and picoscopes).

Alpignano, Italia

Purposes:- Hardware development of a custom Fast Fourier Transform (FFT) core on FPGA Xilinx Zynq-7000 SoC for sonar applications.Tasks:- VHDL-based HDL development and simulation within the Xilinx Vivado Suite 2014.1 tool;- software model verification by utilization of MATLAB and C languages and hardware verification on Zedboard, mounting a Xilinx Zynq-7000 SoC;- technical documentation drafting.Knowledges:- Advanced VHDL-based digital design, simulation and implementation;- advanced dataflow optimization through development of a multicore and pipelined architecture for the IEEE 754 (Floating Point) arithmetic environment;- AMBA AXI-4 and UART communication protocols and interfaces; - advanced application within the Xilinx Vivado Suite 2014.1 tool;- MATLAB-based test pattern generations and model verification;- C language-based driver hardware interface development.

Venaria Reale, Torino, Italy

Purposes:- performance evaluation of the Google Android emulator within the Microsoft Windows environment.Tasks:- research and development about the Google Android framework and operating system;- mobile applications development for Google Android.Knowledges:- Java-based advanced mobile applications development along with utilization and creation of custom graphical interfaces;- professional application within the Eclipse environment;- sensors utilization (accelerometers, gyroscopes);- researching about Global Positioning System (GPS) and IEEE 802.11 (Wireless-Fidelity, WiFi) applications for Google Android.

Computer Engineering Master Degree, Embedded Systems, 108/110

Ingegneria Informatica, 108/110

Piano Nazionale Informatico, 98/100