Eunseok Lee Email and Phone Number

Participated as key layout support with full custom layout generation in full chip. Performed partial Lead blocks, top level routing, floor plan post layout, and NEF extraction to ensure successful delivery to internal and external customers.Completed Projects:• LP4GDDR2, 3/ R+/ x32, x16 combo in 32nm processes (at Nanya)• LP2GDDR2, 3/ R+ / x32, x16 combo in 32nm processes (at Nanya)

Presented a method of layout for new DFM rule. Performed die package check (assembly rules), IO Pad cells (pin/pad placement), blocks and chip floor planning and power plan to deliver all projects on time and on budget. Mentored junior layout designers and provided guidance throughout projects lifecycle.Completed Projects:• TX, RX for 3GHz M-PHY (Message Passing Interface) with LG Inc. in 28nm processes (at TSMC)• DDR3/4 Combo IOs with LG Inc. in 28nm processes (at TSMC)• MIPI (Mobile Processor Interface), Analog M-PHY Module with Zephyrlogic Inc• IP (RX, TX) for 8K D-TV with LG Inc. in 14nm processes (at Intel)

Directed engineering research and development processes for low power, high speed SDR/DDR2, 3 Layouts in transistor level for Dram products. Served as subject matter expert, performing failure analysis at wafer and PKG levels. Assessed project benchmarks through careful exploration and review, and delivered in-depth technical training to teammates. Hand-picked by management to organize checklists and document new Layout / architecture designs, detailing every step during product development process. Key Accomplishments:• Consistently exceeded expectations in coordinating and directing all phases of project-based efforts, motivating and guiding teammates in mass production processes. • Improved operational efficiencies by training teams in new layout design techniques, testing, and failure analysis. • Contributed to the reduction of human error and project time deduction by creating a Skills Pgm.Completed Projects:• 4G DDR3 Project Leader in 21nm and 25nm processes • 2G DDR3 Project Leader and full chip level placement & layout in 29nm processes• 512M DDR3 Project Leader in SKhynix Semiconductor America Inc.• 256M / 512M DDR3 Project Leader and full chip level placement in 54nm processes• 64M / 128M / 1G DDR2 and 3 Project Leader and full chip level placement in 66nm processes• 256M G DDR2 and 3 / 512M / 1G DDR3 Project Leader and full chip level placement in 80nm• Bank (cell array, swd, s/a) area layout in 21nm, 25nm, 29nm, 38nm and 54nm processes• IO path placement & layout in 21nm, 25nm, 29nm, 38nm, 54nm and 66nm processes • ROW and COL path / decorder placement & layout in 80nm, 66nm, 38nm, 25nm and 21nm processes• CMD path placement & layout in 21nm, 25nm, 29nm, 38nm, 54nm and 66nm processes• Voltage / ESD placement & layout in 21nm, 25nm, 29nm, 38nm, 54nm processes• DLL / PLL on a DRAM 21nm, 25nm, 29nm, 38nm, 54nm processes• Auto Cap Generation skill PGM coding for 2G DDR3 in 38nm processes• Completed Environment Setup for Layout project