I have over eight years of experience in fault isolation, failure analysis and reliability enhancement on non-volatile memory media silicon and package. I work with a cross-functional team of engineers, designers, and product managers to provide root-cause analysis and solutions for product quality and reliability issues, as well as support design, product engineering, and development activities.My core competencies include analog and mixed signal IC design and analysis, IC fabrication and process integration, semiconductor characterization, and testing. I have a strong background in electrical engineering, with a BS in Microelectronic Engineering and an MS in Electrical Engineering from Rochester Institute of Technology, where I also conducted research on high frequency VCO design in both 28nm planar and 14nm FinFET PDK’s. I have published my work in the IEEE SOCC conference and have multiple skills in mixed signal design, testing, and characterization, CMOS fabrication and integration, and failure analysis. I know how to leverage my technical skills, domain expertise, and leadership traits to deliver innovative and impactful solutions for my team and organization.