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Evan Jorgensen Email & Phone Number

Senior Semiconductor Quality and Reliability Engineer skilled and experienced in Failure Analysis, Q&R, Devices, Validation, Fabrication and Design. at Intel Corporation
Location: Boise, Idaho, United States 11 work roles 2 schools
1 work email found @intel.com 1 phone found area 304 LinkedIn matched
✓ Verified Jun 2026 4 data sources Profile completeness 100%

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Work email e****@intel.com
Direct phone (304) ***-****
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Current company
Role
Senior Semiconductor Quality and Reliability Engineer skilled and experienced in Failure Analysis, Q&R, Devices, Validation, Fabrication and Design.
Location
Boise, Idaho, United States
Company size

Who is Evan Jorgensen? Overview

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Quick answer

Evan Jorgensen is listed as Senior Semiconductor Quality and Reliability Engineer skilled and experienced in Failure Analysis, Q&R, Devices, Validation, Fabrication and Design. at Intel Corporation, a company with 114813 employees, based in Boise, Idaho, United States. AeroLeads shows a work email signal at intel.com, phone signal with area code 304, and a matched LinkedIn profile for Evan Jorgensen.

Evan Jorgensen previously worked as Senior HBM DRAM Product Quality Engineer at Micron Technology and Senior Failure Analysis R&D Engineer at Intel Corporation. Evan Jorgensen holds Master Of Science (Ms), Electrical Engineering from Rochester Institute Of Technology.

Company email context

Email format at Intel Corporation

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{first}.{last}@intel.com
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Profile bio

About Evan Jorgensen

I have over eight years of experience in fault isolation, failure analysis and reliability enhancement on non-volatile memory media silicon and package. I work with a cross-functional team of engineers, designers, and product managers to provide root-cause analysis and solutions for product quality and reliability issues, as well as support design, product engineering, and development activities.My core competencies include analog and mixed signal IC design and analysis, IC fabrication and process integration, semiconductor characterization, and testing. I have a strong background in electrical engineering, with a BS in Microelectronic Engineering and an MS in Electrical Engineering from Rochester Institute of Technology, where I also conducted research on high frequency VCO design in both 28nm planar and 14nm FinFET PDK’s. I have published my work in the IEEE SOCC conference and have multiple skills in mixed signal design, testing, and characterization, CMOS fabrication and integration, and failure analysis. I know how to leverage my technical skills, domain expertise, and leadership traits to deliver innovative and impactful solutions for my team and organization.

Listed skills include Mixed Signal, Cmos, Analog Circuit Design, Matlab, and 45 others.

Current workplace

Evan Jorgensen's current company

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Intel Corporation
Intel Corporation
Senior Semiconductor Quality and Reliability Engineer skilled and experienced in Failure Analysis, Q&R, Devices, Validation, Fabrication and Design.
Boise, ID, US
Website
Employees
114813
AeroLeads page
11 roles

Evan Jorgensen work experience

A career timeline built from the work history available for this profile.

Senior Hbm Dram Product Quality Engineer

Current

Boise, Idaho, US

Helping to achieve best in class Quality and Reliability of Micron’s HBM DRAM products. Planning and execution of product reliability qualifications, associated data analysis and automation, disposition of failures, and driving corrective and preventative actions to enhance quality and reliability.

Jan 2024 - Present

Senior Failure Analysis R&D Engineer

Santa Clara, California, US

Conduct Fault Isolation and Failure Analysis in support of Product Quality and Reliability, Design, Product Engineering, and Development on non-volatile memory media silicon and package. Supervise PFA technicians. Procure lab equipment. Manage lab equipment and infrastructure. A wide variety of skills from areas of analog and mixed signal IC design and.

Feb 2016 - Jan 2024

Ic Layout Engineer

San Jose, California, US

Use Cadence full-custom EDA tools for physical design of analog and mixed signal blocks in Touch and Display Driver Integration SoC for mobile platforms as well as support for touch sensor ID system. Attend design reviews and make applicable layout modifications based on review. Work with designers to minimize parasitics, coupling and noise on sensitive.

Jun 2015 - Jan 2016

Graduate Research Assistant

Rochester, NY, US

Conducted research for my thesis project on high frequency VCO design in 28 nm CMOS technology (details below in project section, as well as thesis).Served as a lab TA for the Analog and Mixed Signal IC Design course.

Jun 2014 - Jun 2015

Lab Assistant

Center For Detectors

CfD designs, develops, and implements new advanced sensor technologies through collaboration with academic researchers, industry engineers, government scientists, and university/college students.General lab engineering and technical duties; assisting engineers in the lab.

Sep 2012 - Apr 2013

Co-Op Rf/Microwave Engineer

Falls Church, VA, US

RF and Microwave design, RF testing, advanced material characterization, layout and design supporting advanced integration process development.

Jun 2012 - Sep 2012

Ic Layout Co-Op Engineer

San Jose, California, US

Use Cadence full-custom EDA tools for physical design of analog and mixed signal blocks in Touch and Display Driver Integration SoC for mobile platforms as well as support for touch sensor ID system.

Jun 2011 - Mar 2012

Co-Op Test Engineer

Nantero, Inc

Worked on all phases of testing and characterizing CNT based memory devices.

Sep 2010 - Feb 2011

Maintenance Crew/Crew Leader

Ferguson Management Company

Directed and supervised maintenance crews. General maintenance duties.

Jan 2007 - Jan 2009

Snowboard Instructor

Winterplace Ski Resort

Winters 2005 to 2008.Taught people of all experience levels and ages, gave private and group lessons, trained instructors.

Dec 2005 - Apr 2008
Team & coworkers

Colleagues at Intel Corporation

Other employees you can reach at intel.com. View company contacts for 114813 employees →

2 education records

Evan Jorgensen education

Master Of Science (Ms), Electrical Engineering

Rochester Institute Of Technology

Bachelor Of Science (Bs), Microelectronic Engineering

Rochester Institute Of Technology
FAQ

Frequently asked questions about Evan Jorgensen

Quick answers generated from the profile data available on this page.

What company does Evan Jorgensen work for?

Evan Jorgensen works for Intel Corporation.

What is Evan Jorgensen's role at Intel Corporation?

Evan Jorgensen is listed as Senior Semiconductor Quality and Reliability Engineer skilled and experienced in Failure Analysis, Q&R, Devices, Validation, Fabrication and Design. at Intel Corporation.

What is Evan Jorgensen's email address?

AeroLeads has found 1 work email signal at @intel.com for Evan Jorgensen at Intel Corporation.

What is Evan Jorgensen's phone number?

AeroLeads has found 1 phone signal(s) with area code 304 for Evan Jorgensen at Intel Corporation.

Where is Evan Jorgensen based?

Evan Jorgensen is based in Boise, Idaho, United States while working with Intel Corporation.

What companies has Evan Jorgensen worked for?

Evan Jorgensen has worked for Intel Corporation, Micron Technology, Synaptics, Rochester Institute Of Technology, and Center For Detectors.

Who are Evan Jorgensen's colleagues at Intel Corporation?

Evan Jorgensen's colleagues at Intel Corporation include Gong Jinlong, Agustin Mayorga, Renjini J., Song Yoong Siang, and Sangeri Lakshmi.

How can I contact Evan Jorgensen?

You can use AeroLeads to view verified contact signals for Evan Jorgensen at Intel Corporation, including work email, phone, and LinkedIn data when available.

What schools did Evan Jorgensen attend?

Evan Jorgensen holds Master Of Science (Ms), Electrical Engineering from Rochester Institute Of Technology.

What skills is Evan Jorgensen known for?

Evan Jorgensen is listed with skills including Mixed Signal, Cmos, Analog Circuit Design, Matlab, Cadence Virtuoso, Semiconductors, Electronics, and Circuit Design.

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