- Micro Architect and RTL Design (Future Core): Working on a Future Intel Core, focusing on the Instruction Fetch and Decode part of core.- AVX Cross-cluster VT Lead (Xeon Phi - Knights Landing, Knights Mill, Knights Hill): o Led the cross cluster design and pre-silicon validation team that implemented AVX1, AVX2 and AVX-512 instructions on Knights* projects to deliver on time RTL design. o Created staging plan based on cross cluster RTL and val dependencies. Defined stage exit criteria, wrote assembly template for basic coverage tests, setup cross cluster testplans.- RTL Power CZAR (Knightshill) - Picked up the RTL Power CZAR duties to first get a better handle on Core power and then partnered with SD Power CZAR to run a focused dungeon to improve both dynamic and leakage power. The team achieved over 10% power saving in PTPX over a 3 month dungeon. - Design Lead FEC Cluster (Xeon Phi - Knights Landing, Knights Hill): o Partnered with the Architecture team on definition of various features. Played a critical role in micro architectural definitions, investigation of the area and power costs to help guide on optimal implementation choices. o Led the RTL effort for feature implementation and design convergence. Guided and worked on timing and power convergence in addition to the focus feature implementation and functional health. Functional areas focused on Instruction decode and guidance on multi-threading and branch prediction enhancement.- Micro Architect and Logic Designer (Larrabee, Knights Corner): Worked on Micro Architecture and logic implmenetation on MIC Cores. Worked on definition and logic implementation, timing and power optimization for threading, Control Register Bus and other areas of the core.

- Microcode Architect (Westmere Feature PF, TR): During pathfinding phase, analyzed various microcode focused features proposals and recommended candidates for the TR phase. During TR phase, took part in features definition, and prototyped likely candidates using patches as well as experiments on Pre-si models.- Microcode Design Engineer (Pentium 4 - Cedarmill: Design and implemented microcode for VT enhancements, Power Management, Patch loader, Control Register interfaces and feature enumeration. - Microcode Validation Engineer (Pentium4 - Prescott): Owned validation of FP, SSE areas and interactions w/ EXEC and RRRR H/W clusters.

Project lead on PCI/PXI 6534 (Data Acquisition and Pattern I/O board) and designed the PCB and implemented the firmware logic using FPGA.