• As a CMMS and Electrical Engineer, I am responsible to manage and keep update on ADeM and SAP PM and maintaining the Gas Utilities and CDA. To ensure all SAP PM and items maintained as per schedule and close accordingly.• To organise team to ensure PM activity carry out as per SAP PM schedule. All PM activity should be verified and upload into SAP.• Analyse and update SPC operations stability for weekly presentation. Coordinate with related system owner on improvement planned for alignment during presentation.• Interface with Engineering, Operation, EHS for equipment, preventive / correction maintenance program and projects & compliance with various regulatory procedures.• Monitoring the Building Automation System (BAS).• Analyse the high alarm and trending of the system and detect if there any unusual pattern.• Update the FMECA to improved designs for products and processes, resulting in higher reliability, better quality, increased safety, enhanced customer satisfaction and reduced costs.• Document controllers, manage and oversee documents for a particular project or for an entire organization. They ensure the proper documents are created and signed, that all data is accurate and that documents are stored and backed up and any retention policies are followed.

As a Design Engineer I am entrusted with the Integrated Circuit (IC) design layout from the system level definition to Backend implementationTasks that I am responsible are:• Taped out designs with numerous foundries worldwide – TSMC, IBM, Silterra, XFAB, MIMOS, ALTIS• Experience with the following tools: Cadence Virtuoso (Layout), PVS, Calibre Verification• Background in analog layout designs like ADC, DAC, oscillators, regulators, PLLs, op-amps, comparators, current mirrors, active-loads, voltage regulators, charge pumps, etc.• Fullchips or block level integration of mixed signal GDS.• Strong problem-solving ability• Deep sub-micron process design experienced. Up to 14nm is preferable.• Understanding of circuit principles as affected by layout such capacitance, speed noise & electro migration.• Work on custom analog, digital and mxed signal layout IPs such as ADC, DAC, oscillators, regulators, LDO, DC-DC and PLLs• Capable of block or fullchip level floor planning in analog / mixed signal design.• Have done multiple tapeouts and proven records of designing complex ICs / IPs in state of the art CMOS process technologies and has successfully placed products / IPs into production, preferably multiple times• High level proficiency in performing physical verification check (DRC, ERC, LVS, NATENNA, rules) with PVS/Calibre tools.Has served Altis Semiconductor company, X-FAB Group (Exchange), SilTerra Malaysia, Mimos and Xilinx Inc. on a project in designing Layout and services support for the partner companies.

I have also completed the SL1M Programme with TNB, it’s a program on young graduate enhancement scheme for a period of 1 year. I was attached with TNB under Transmission Line Projects group, where I learnt a lot about the transmission of power system, installation of transformer and testing of the electrical power equipment.