Farouk Khaled Email & Phone Number

Cairo, Cairo Governorate, Eg

Cairo, Egypt

Digital design project for compute express link [CXL]: design for high performance data center computer itincludes PCIE cxl.io and 2 additional main blocks CXL.cache allows peripheral devices to coherently access andcache host CPU memory with a low latency request/response interface. CXL.mem: allows host CPU tocoherently access cached device memory with load/store commands.

Throughout this Diploma, I had the opportunity to dive deep into crucial topics in this challenging field, including:🔹SystemVerilog Datatypes and threading🔹 SystemVerilog Interfaces and subroutines🔹 Developing a verification plan and extracting design requirements🔹 Understanding and analyzing RTL code coverage results🔹 Implementing a functional coverage model🔹 Developing SystemVerilog assertions🔹 Basics of Object-Oriented Programming🔹 Generating constrained random stimulus🔹 Simulation-based verification techniques using UVM🔹 Gaining knowledge of UVM structures, components, sequences, and

Content:- Efficient RTL Coding Using Verilog language- Building Advanced Self-checking Verilog Test-bench- TCL Scripting Language- Static Timing Analysis- Low Power Design Techniques- Clock Domain Crossing- RTL Synthesis on Design Compiler- Design For Testing (DFT) Insertion- Formal Verification Post-Synthesis & Post-DFT & Post-PnR- ASIC Flow including (Floorplanning, Pin Placement, Clock Tree Synthesis, Placement, Routing, Timing Closure, Chip Finishing, Sign Off) - Post-Layout Verification (Gate Level Simulation)o Final Project: “RTL to GDS Implementation of Low Power Configurable Multi Clock Digital System” - Description: It is responsible of receiving commands through UART receiver to do different system functions as register file reading/writing or doing some processing using ALU block and send result as well as CRC bits of result using 4 bytes frame through UART transmitter communication protocol. - Project phases:-- RTL Design From Scratch of system blocks (ALU, Register File, Synchronous FIFO, Integer Clock Divider, Clock Gating, Synchronizers, Main Controller, UART TX, UART RX).- Integrate and verify functionality through self checking testbench. - Constraining the system using synthesis TCL scripts.- Synthesize and optimize the design using design compiler tool.- Analyze Timing paths and fix setup and hold violations.- Verify Functionality equivalence using Formality tool- Physical implementation of the system passing through ASIC flow phases and generate the GDS File.- Verify functionality post-layout considering the actual delays.

Egypt