- Over 12 years of relevant industry experience and technical leadership in defining, implementing and validating high performance and low power DSP/FEC engines used in modern optical transceivers (100 Gbps per Lambda), enterprise-level HDD/SSD controllers (30 Gbps effective throughput) and high-throughput wireless/wired PHY/MAC layers of various IEEE standards on high-volume industry-leader ASICs covering technologies ranging from 65nm down to 7nm. - Deep theoretical and practical understanding of all components in a digital communication and storage system including Timing Recovery Loops, Equalization (FFE/DFE), LMS, FFT, MLSD, SOVA- Expert in FEC encoder/decoder architectures including Algebraic codes (BCH/Reed Solomonbased on Berlekamp Massey/Extended Euclidean and Chien search) and graph codes (LDPC/Turbo with flooded/layered decoders). Perfect understanding of the trade-offs governing different FEC's performance, throughput, latency and complexity. - Extensive experience in design and implementation of core IPs in power-line communication MAC layer including highly-sensitive network scheduler (consisting of both CSMA-CA and TDMA periods), network timing synchronization, packet transmission/reception and data queue management schemes - Good understanding of different cryptosystem algorithms and architectures including symmetric encryption/decryption (DES, 3DES, AES), asymmetric encryption/decryption (RSA, Diffie-Hellman, Elliptic Curves), digital signatures and SHA functions- Hands-on experience with all stages of an ASIC flow including system architecture definition, RTL implementation/simulation/verification, logic synthesis, gate level simulation (for accurate power measurement and estimation), Lint, logic equivalence checking, clock domain crossing, static timing analysis and to a lesser degree Place and Route- Fluent in System Verilog, Python, C/C++, Matlab- Extremely strong in oral and written communication