Signal Integrity/Power Integrity Analysis And Fpga Senior Project Manager
10Gbps up to 800Gbps data center Ethernet Switch's NRZ/PAM4 differential signal integrity simulation and analysis, including pre-sim, layout constraint, post-sim and PCB layout quality assurance and improvement. Target to meet IEEE 802.3 CD/BS channel loss constraints and CAUI/GAUI eye openings with the lowest cost PCB material and stackup as well as TX.