SoulStec provides leading edge semiconductor consultation, design services and complete solutions to get customers products to market. This solution spans from Design conception to Chip realization and can be grouped into front-end, back-end and fabrication development Cycle.www.soulstec.com

Key Achievements• Proposed and developed a virtual prototyping environment using Graphical UML based framework on a 16 core machine of the SoC to aid the software bring-up.• Design and facilitated the fabrication of hardware prototype of the PMR system using multiple Altera Cyclone V FPGA devices to model the SoC.• Integrate standard UVM/OVM libraries and develop proprietary systemVerilog UVM/OVM libraries for IP, bus network and ASIC/SoC verification.• Build up, Managed and… Show more Key Achievements• Proposed and developed a virtual prototyping environment using Graphical UML based framework on a 16 core machine of the SoC to aid the software bring-up.• Design and facilitated the fabrication of hardware prototype of the PMR system using multiple Altera Cyclone V FPGA devices to model the SoC.• Integrate standard UVM/OVM libraries and develop proprietary systemVerilog UVM/OVM libraries for IP, bus network and ASIC/SoC verification.• Build up, Managed and lead a team of 16 top quality SoC designer and verification engineer to develop a 3rd Generation market leading PMR solution. • Worked directly with the CTO and Product development director to specify, architect and roadmap the PMR SoC based on market needs and technology roadmap.• Specified the verification, emulation and validation approach (EDA tools, Prototyping and silicon validation platform) adopted for the development of the SoC.• Defined and implemented the SoC test Framework which is also adopted by the production SW development team.• Design an automated documentation process for both the SoC development and SW team. Show less

Key Achievements• Define (by performing performance modelling of the data throughput, MIPS and co-processor accelerator) and Implemented (using System C and Verilog) a 3D graphics engine architecture which is now used in most popular brands 3D Full-HD TVs.• Developed SoC IO STA flow using Cadence ETS interfaced with PERL and EXCEL/VBA. This flow is now adopted as standard within the company. • Architected bandwidth and latency optimisation methodology, which is used for processor… Show more Key Achievements• Define (by performing performance modelling of the data throughput, MIPS and co-processor accelerator) and Implemented (using System C and Verilog) a 3D graphics engine architecture which is now used in most popular brands 3D Full-HD TVs.• Developed SoC IO STA flow using Cadence ETS interfaced with PERL and EXCEL/VBA. This flow is now adopted as standard within the company. • Architected bandwidth and latency optimisation methodology, which is used for processor and buffer size criteria for a Full-HD-DTV SoC. The methodology is adoptable for any SoC solution.• Studied and re-architect a mixed-signal RFID ASIC to achieve a 50% communication range improvement. The proposed solution was modelled in Matlab and realised in a CmoS13 process based test chip. This solution is now adopted for the future generation of key-fobs ASICs within NXP.• Create a SpyGlass template for power domain crossing check, power estimate and power reduction analysis. The results are then used as power budget estimate for key IPs within the SoC.• Designed an automated clock generation IP build flow for a full HD-DTV SoC with EXCEL/VBA. The flow supports multiple power domains, multiple PLL types and all DFT algorithms for the SoC. The flow generates the IP in both VHDL and VERILOG. Show less