Fernando Castillo Email & Phone Number

Technical lead, deployed and helped customers gain success using Veloce Emulation platforms. Bring up included multi-billion gate designs in Virtual and ICE solutions. Focus on SoC design bring up, ARM and x86 based designs.Deployed solutions e.g. Virtual Ethernet, Virtual PCIe, iSolve PCIe, UART, JTagCreated custom test bench solutions using Veloce TBX technology and standard DPI.Supported and deployed QEMU based virtual ARM solutions.

San Jose, California, Us

Worked with Fortune 500 companies, supporting embedded software and emulation teams. Focused on large SOC environments, specializing in simulation acceleration.Trained customers to write acceleratable BFMs (Bus Functional Models), becoming part of their team, with the goal of bringing designs up on Palladium I, Palladium XP, and Palladium Z1. BFMs built using industry standard interfaces such as SCEMI, UVM, DPI, SystemC, and Signal Based. Deployed various use models, Dynamic Power Analysis (DPA), Low Power Flow (UDP), Coverage (Code + Toggle).Creation of new flows to assure customer success, for example writing a BFM to interconnect between Virtio magic ‘C’ to Palladium using a TCP/IP socket approach.Brought up large SOC designs in ICE mode using speedbridges. Interfaces have included UART, JTAG, SATA, PCIE. Managed accounts on technical side, duties include setting proper expectations, initial discovery, design compile, integrating peripheral interfaces, design debug/bring up, creating testcases, coordinating between RnD and customer.DAC (Design Automation Conference) Booth PresenterAcceleratable UVM InstructorPalladium (XP/Z1) Instructor

San Jose, California, Us

Responsible for helping customers develop OVM/UVM testbenches using Incisive.Testbench development focused on functional coverage, code coverage, assertions.Worked with customers to convert VMM environment to OVM/UVM environmentsUVM/OVM InstructorSystemVerilog Instructor

San Jose, California, Us

Delivered SystemC/VIC/testbuilder/C++ contractual services for Cadence. Wrote BFM’s (Bus Functional Models) in C++ (Testbuilder/SystemC/SCV), alongside customer verification teams.Took part on the development team for the Cadence Verification IP (in C++). Part of a team that wrote the AMBA (AHB/APB) TVMs (Transaction Verification Models). Development was done with testbuilder, a C++ class library and used PLI/VPI for interfacing to the simulator.SystemC/SCV Instructor, focusing on building skillsets to deliver verification environments.C++ Instructor, focused on training customers on basic C++ topics.

Santa Clara, California, Us

Developed verification environment and methodology for the full chip team, from scratch. Wrote XGMII, PCS (Physical Coding Sublayer) interfaces, using Specman ‘e’ and Verilog. Specman code included BFMs (Bus Functional Models), Tx/Rx Monitors, and a self-checking test bench using a scoreboard. Monitors broken up into ’e’ and Verilog components. Duties included creating testplans, assertions, and debug.Responsible for fully automating verification environment, integrating various CAD tools using perl.

Santa Clara, California, Us

i740 and i810 chipset Graphics Designer, responsible for carrying design from Micro Architecture specification to RTL for graphics Cache controller. Duties included documentation, RTL design, writing tests, performing logic validation, Synthesis, Static Timing Analysis, and Gate Level Simulation.i810 chipset Verification Lead for partial full chip. Defined and implemented a methodology for seamless integration of vendor tool flows with a C++ high level model. Methodology included compiling of design, running tests, automating notifications, and debug automation. Managed high quality model releases to full chip validation team.

Santa Clara, California, Us