Technical Project Manager managing teams ranging from 7 to 16 members. I was one of the project managers of a 4-year project with up to few hundred people in global remote teams with a goal to develop power efficient hybrid software/hardware co-designed architectures that use dynamic binary translation.Within the same project, I was the Lead Architect of its first CPU hardware specification. Later, led the memory organization and hardware support for multicore including coherency/consistency protocols, transactional memory-like support and consistency of translated code. Leading the definition of the memory organization implied leading a multidisciplinary group comprising software architects, hardware architects, validation engineers, and hardware designers. In the final stage, I also led the hardware definition to support out-of-order execution including renaming, reservation stations, wakeup logic, retirement, etc. In parallel, I managed and was Lead Architect of a project which goal was to provide very high energy efficient hardware support for cognitive computing related algorithms, and especially focused on convolutional neural networks for visual computing. I also led activities related to understanding the way new devices based on spin could be used to improve existing general purpose architectures and specialized architectures.Tools used: C and C++ to develop and modify complex highly detailed in-house software simulators that model experimental processor designs, product quality dynamic binary optimizers and simics for multiprocessor functional emulation. Scripting languages like perl, python, shell script or VB for data analysis; gnuplot and latex.

During this period I led a project of 5 people on dynamic auto-parallelization of single-threaded applications in order to exploit multi-core capabilities on sequential code. I also led the exploration of hardware extensions to support speculative dynamic binary optimization on simple in-order cores with minimum overhead.

When I joined Intel Labs I worked on several projects where the main target was to investigate and develop IP (Intellectual Property) on techniques that could be utilized to implement scalable high performance and power efficient general purpose multi-core/multi-threaded processors. The focus of my research was on simultaneous multithreading techniques for in-order and out-of-order cores, reconfigurable multi-core designs and organizations with clustered memory and execution resources.During this period I also collaborated with the design teams on some of the biggest micro-architectural changes performed on the Intel Core architecture when transitioned from Nehalem to SandyBridge.