Jeff Fitzgerald Email & Phone Number

Sunnyvale, CA, US

Functional/Structural verification lead for enterprise class microprocessor product family. Drove logic validation of pervasive Globals design features and functions. Developed feature verification schedule and milestone plans in-line with project requirements. Defined resource deployment plans to optimize project execution targets with individual growth.

Developed educational programs to teach children computer science fundamentals using low cost MCUs.

Santa Clara, California, US

• Overall functional leadership, strategy / vision, execution lead for Structural Test (ATPG) and Test / Debug Verification for High Performance CPU organization. Successful project and feature execution from development.
• Managed geographically diverse team of 20+ Structural Test and Design for Test Verification professionals
• Led deployment and integration of new CAD tooling capabilities into design RTL and integrations development flows to ensure test feature predictability and project success.
• Defined Structural Test milestone timeline and deliverables for AMD wide design map program management system.
• Formulation, coordination and co-driver of Team Mentorship program for Sunnyvale Microprocessor Core design organization.

• Led Test Applications team responsible for development, debug and qualification of HaL SPARC v9 microprocessor test specifications/deliverables. Established team budgets, goals/plans/schedules and personnel.
• Prototype debug and characterization of microprocessor designs 1st level failure analysis on all designs. Device process geometries ranging from 0.5um thru 180nm.
• Specification of DFT features (LSSD, JTAG, Memory BIST, Logic BIST and Burn-in features).
• Verification of DFT feature set thru VCS vector simulation.
• Creation/validation of full test program suite, including ATPG, BIST, DC parametric and functional test suite in Fujitsu Test Description Language (FTDL) and Advantest pattern formats.
• Primary interface to Fujitsu Semiconductor and Technology groups regarding product test and failure analysis issues. Sustaining support for production microprocessor designs.

Responsible for prototype characterization/production test program release of all device technology families. Developed wafer test emulation shell to validate ATPG modes and vectors.Coordinated first release of ATPG vector translation software for Toshiba’s CAT System for device testing on Advantest T3340 testers. Interacted with overseas engineering teams.

Developed all production structural tests for high performance RISC deigns. Wrote control interface for parametric test system and characterized prototype designs.