Jeff Fitzgerald Email & Phone Number

Sunnyvale, Ca, Us

Functional/Structural verification lead for enterprise class microprocessor product family. Drove logic validation of pervasive Globals design features and functions. Developed feature verification schedule and milestone plans in-line with project requirements. Defined resource deployment plans to optimize project execution targets with individual growth objectives. Successful pre and post silicon project execution across SPARC based Enterprise and Cloud products.* Managed diverse engineering team of senior and junior talent levels across geographically distributed regions. Provided guidance and direction to meet project objectives.* Led schedule development, tracking and completion for high profile Globals design features and functions, including Clocking, Connectivity, Debug, General Purpose Registers, I/O, Power Management, Reset, SerDes, Testability (JTAG/MBIST/Scan) and Reset. Instituted key milestone and metric driven project tracking to ensure project priorities are well managed.* Introduced formal assertion based connectivity solution to drive early functional exposure to connection issues yielding higher functional verification productivity. * Coordinated cross functional debug team to resolve post-silicon functional failures. Worked between design and product team partners to root-cause tester hardware discrepancy.

Developed educational programs to teach children computer science fundamentals using low cost MCUs.

Santa Clara, California, Us

Overall functional leadership, strategy / vision, execution lead for Structural Test (ATPG) and Test / Debug Verification for High Performance CPU organization. Successful project and feature execution from development through production across 5 generations and all variants of microprocessor designs spanning 130nm-32nm process nodes, including Athlon/Opteron (K8) and Trinity product families. Delivered high quality ATPG test results.• Managed geographically diverse team of 20+ Structural Test and Design for Test Verification professionals• Led deployment and integration of new CAD tooling capabilities into design RTL and integrations development flows to ensure test feature predictability and project success. • Defined Structural Test milestone timeline and deliverables for AMD wide design map program management system.• Formulation, coordination and co-driver of Team Mentorship program for Sunnyvale Microprocessor Core design organization.

Led Test Applications team responsible for development, debug and qualification of HaL SPARC v9 microprocessor test specifications/deliverables. Established team budgets, goals/plans/schedules and personnel evaluations. Development responsibilities included:• Prototype debug and characterization of microprocessor designs 1st level failure analysis on all designs. Device process geometries ranging from 0.5um thru 180nm.• Specification of DFT features (LSSD, JTAG, Memory BIST, Logic BIST and Burn-in features).• Verification of DFT feature set thru VCS vector simulation.• Creation/validation of full test program suite, including ATPG, BIST, DC parametric and functional test suite in Fujitsu Test Description Language (FTDL) and Advantest pattern formats.• Primary interface to Fujitsu Semiconductor and Technology groups regarding product test and failure analysis issues. Sustaining support for production microprocessor designs.• Established and managed product engineering test and characterization failure analysis lab. Led lab design, equipment procurement, qualification and integration of new test equipment, including Advantest T6672 logic test system• Generated chip level test programs for HaL Microprocessor MCM designs; CPU, CACHE & MMU, I/O ASICs and memory controllers

Responsible for prototype characterization/production test program release of all device technology families. Developed wafer test emulation shell to validate ATPG modes and vectors.Coordinated first release of ATPG vector translation software for Toshiba’s CAT System for device testing on Advantest T3340 testers. Interacted with overseas engineering teams and brought up initial capabilities in Japan facility.

Developed all production structural tests for high performance RISC deigns. Wrote control interface for parametric test system and characterized prototype designs.