Francesc Serra-Graells Email & Phone Number

My research is focused on the design of low-power mixed-signal CMOS circuits for advanced sensing systems. The motivation of this research line is double. First, the lack of portable and miniaturized energy sources for ubiquitous integrated circuits means that very low-power design techniques are of high interest. Second, the global More than Moore trending reinforces CMOS technologies as the most economical option not only for the integration of electronic circuits but also for truly heterogeneous systems-on-chip (SoCs) with sensing capabilities. My works on low-power (low-voltage and/or low-current) CMOS circuit design have been extended to a wide variety of analog, mixed-signal and RF functional blocks, such as amplifiers with automatic gain control (AGC), analog-to-digital (ADC) and digital-to analog (DAC) data converters, voltage controlled oscillators (VCOs) in phase-locked loops (PLLs) and power management units (PMUs), among others. The results have been employed in the development of full-custom application-specific integrated circuits (ASICs) and IP library blocks in several CMOS technology nodes (2.5um, 1.2um, 0.8um, 0.35um, 0.18um, 65nm and 22nm) for very low-power smart sensing applications, like hearing aids, IR and X-ray image sensors, MEMS and chemical microsensors, implantable systems for neural recording, aerospace instrumentation and strategic equipment. I always try to maintain a good balance between the above research work and development activities in the form of contracts and patents for transferring technology to industrial partners. It is also worth to highlight the projection of my R&D experience towards IC reverse engineering and teaching innovation at university.

Listed skills include Cmos, Asic, Microelectronics, Ic, and 14 others.