Frank Creed Email & Phone Number

Massachusetts, United States

• Coordinated and trained remote team on full-chip layout verification flow to complete “mock” tape-in ahead of schedule, to provide confidence in meeting overall project layout convergence for 7nm server chip. Executed.
• Spearheaded full-chip layout convergence team, reduced job run time by 37%, verified new process variant, automated weekly layout error tracking progress, ran/triaged/directed layout fixes for 7nm server chip to.
• Investigated and resolved DRC latch-up differences between design steppings, isolated cause to change in run mode (rotated vs non-rotated die), which eliminated the risk of any required fixes that could compromise.
• Mitigated dedicated datacenter compute bottlenecks and long job wait times by benchmarking and planning critical compute capacity improvements, trained 100+ internal and contract engineers on best usage practices of.
• Generated detailed die-to-die routing diagram from architectural spec to help solidify sub-system floorplans and quantify die-to-die latency to help meet overall system performance targets for custom 7nm server chip.
• Simulated and optimized best routing/repeater strategy for system-critical wide bus to meet demanding program performance goals for custom 14nm server chip.

• Designed dual mode 3.3v/1.8v tolerant I2C receiver for Haswell PCH based on an urgent request late in design cycle to enable lower voltage peripherals, simplify the platform, and save Bill-of-Material (BoM) costs.
• Received division award for saving $16M by creative floorplanning to enable significant additional content without increasing die size for Broadwell PCH.
• Received division award for identifying and implementing power reduction for Broadwell PCH, including discovering and decreasing leakage by >80% in Real Time Clock voltage regulator to fulfill power reduction goal.
• Received division award for design and execution of analog test chip to verify circuits and achieve first-pass silicon success in new 32nm process variant for Haswell PCH: drove floorplan to enable smaller die than.

• Analog circuit design for high-speed memory interfaces
• Received award as project lead for coordinating test chip to evaluate circuit topologies in new 45nm process and ensuring on-time delivery to external foundry partner.
• Designed 2 variants of 45nm linear CMOS voltage regulator. Delivered blocks on-time and within spec, even though requirements changed and constraints were tightened during project.
• Member of division-wide task force to unify ESD designs across all PHY teams. Helped develop common simulation suite, and used it to identify and fix false triggering problem.

• Custom circuit design for I/O and ESD blocks, high speed differential receivers (LVDS, Serial-ATA)
• Received award and customer commendation for successfully debugging critical noise problems with 0.2um LVDS receiver on prototype system board.
• Designed LVDS receivers in multiple processes with different circuit topologies (1 patent pending) to satisfy application-specific customer requirements.
• Received award for meeting aggressive schedule and area targets in designing a family of unique ESD pads to differentiate customer's product offering.

• Custom I/O, ESD, standard cell circuit design
• Successfully debugged write strobe pulse width problem on 0.35um custom RAM, to help customer run silicon at higher clock frequencies than original application.

• Circuit designer for Content-Addressable-Memory blocks
• Accelerated completion schedule 4 weeks by employing Cadence Layout Synthesis (LAS) to auto-generate clock circuits. Collaborated with Cadence LAS developer to significantly improve the quality and reliability of the.
• Decreased CAM macro area by 5% by using IC Craftsman router, worked with Cadence developers to debug IC Craftsman to Virtuoso interface.
• Conceived, developed and optimized memory array and all associated circuits (word line & bit line drivers, sense amp, match circuits, precharge circuits) for company's first internally designed 0.35um CAM products.
• Set up design infrastructure: selected workstations, evaluated CAD software, trained layout engineers in physical verification tools and developed parasitic extraction flow.

• DRAM circuit designer
• Received patent for front-end interface circuits to improve performance for 8Mb DRAM macro in an integrated L2 cache, which was IBM's first embedded DRAM product.
• Conceived 3T DRAM subarray in between projects to increase memory density available in 0.5um logic process. Designed, simulated and laid out cell, current sense amp and bi-directional data circuit to prove feasibility.
• Beta tester for internally developed layout automation tools. Identified missing functionality and prioritized designers' needs, debugged code problems and provided detailed feedback to developers. As liaison between.

• Bipolar test/characterization engineer
• Received award as project leader and test engineer for bipolar SRAM prototype evaluation. Drove development of complex hardware/software tests to characterize critical timing data, which was used to implement changes.
• Developed original solutions for device cooling and automated data analysis to streamline testing, reduce data turnaround time and improve data quality.