Francisco Ramirez

Francisco Ramirez Email and Phone Number

Engineering Manager @ Intel Corporation
santa clara, california, united states
Francisco Ramirez's Location
Guadalajara, Jalisco, Mexico, Mexico
About Francisco Ramirez

Mechanical Engineer Manager with expertise in product design and project management activities. Capable to lead engineers in projects that include product design, simulations, prototype testing, drawings creation using GD&T, BOM creation, FEA analysis, thermal analysis and stack-up analysis. Experience working with AGILE philosophy as a Product Owner of a SCRUM team planning team activities according with the feature party per release checking the project progress daily with a tracking tool called Rally. Abel to work as a people manager with experience managing group of engineers and technicians. Focused on innovation having five USA patents, two tread secrets, eight DTTC papers and 3 more IDF’s applications under consideration.

Francisco Ramirez's Current Company Details
Intel Corporation

Intel Corporation

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Engineering Manager
santa clara, california, united states
Website:
intel.com
Employees:
133841
Francisco Ramirez Work Experience Details
  • Intel Corporation
    Program Manager For Electrical Validation Group
    Intel Corporation Sep 2020 - Present
    Guadalajara, Mexico Metropolitan Area
    Program manager for Electrical Validation team in charge of the full electrical validation of the future silicone for server programs. Responsible to set product requirements based on customer expectations.I am responsible for creating validation schedule and program indicators, plan equipment for testing and tracking program milestones. Responsible for plan laboratory needs like electricity, air compressed and special needs for testing. Follow up on thermo-mechanical needs to match with product requirements.Responsible to set up weekly meetings in post testing and Power On testing.Responsible for sitting tracking in a database to track sitting del¡velopment until its closure
  • Intel Corporation
    Mechanical Engineer Manager
    Intel Corporation Sep 2013 - Oct 2022
    Zapopan, Jalisco, Mexico
    This group is responsible for the design and implementation of validation sockets and thermal mechanical systems for next generation CPUs and memory packages. Responsible for continuing having a strong GDC mechanical team and driving the qualification of new socket technologies to address future validation challenges. Created a learning and integration plan for new hires to train the new mechanical engineers in group design methodologies and design processes. Providing day to day coaching and mentorship to the new hires to bring them to the expected productivity level. Used to have weekly 1 to 1 with the team members providing regular performance feedback to the team members and set job level expectations. I used to evaluate the gaps in technical and soft skills and arranged training classes to the team. Led team building initiatives and implemented Strengths Finder session to the team to understand the team orientation and strengths. I performed evaluations and development plan for the team, focused on a cross training activity learning thermal simulations and debug design.Senior Mechanical Engineer (September 2008 – May 2013)I owned the development of validation sockets, Interposer hardware and mechanical retentions for the entire server program. I presented socket development updates in different forums and Geos.
  • Intel Corporation
    Project Manager Scrum Master
    Intel Corporation Jan 2013 - 2018
    Zapopan, Jalisco, Mexico
    Experience working with AGILE philosophy as a Product Owner of a SCRUM team planning team activities according with the feature party per release checking the project progress daily with a tracking tool called Rally.
  • Intel Corporation
    Senior Mechanical Design Engineer
    Intel Corporation Sep 2008 - May 2013
    Zapopan, Jalisco, Mexico
    I owned the development of validation sockets; Interposer hardware and mechanical retentions designs for server programs. I presented socket development updates in different forums, engaged with package designer’s team, lead engineers, platform architects and program managers across multiple organizations and led weekly socket working group meetings. Developed the thermo-mechanical retention hardware for Server package and Pre-Power On interposer leveraging from other solution. I performed structural analysis using ANSYS software, completing the hardware testing and delivered a robust mechanical solution for Pre-Power On needs, developed and executed a mechanical validation plan.I delivered the installation instructions manuals for all thermos-mechanical solutions. I delivered to Intel my designs plus innovation to Intel during my work as a mechanical engineer, next is a list of those: Innovation, Technical publications and IDF’s at Intel.DTTC Paper accepted for Publication internally at Intel:• OPIO test mezzanine card solution for KNL• Innovative Mechanical and Thermal Solutions for Knights Corner• MPI Socketed Systems MPI Socket Mechanical, Electrical Modeling and cost Analysis in DVP• Mid-Bus Probing Interposer Solution for KNC-GDDR5 Memory Channel• Mechanical and Electrical design solution for KNC Package top side probing• Knights family thermo-mechanical design evolution in post-silicon validation• First Ever Multi-PoP Socket and Its Role in Reducing KNL Post-Si Validation Time• Breakthrough Validation Socket Technologies for Form Factor and OEM Boards
  • Continental
    Mechanical Development Engineer
    Continental Sep 2007 - Sep 2008
    Tlaquepaque, Jalisco, Mexico
    I worked as a mechanical engineer in the CV (Commercial Vehicles) department, in charge of the Freightliner and Mack Trucks instrument clusters doing new product quotations and soling manufacturing problems.
  • Soles
    Mechanical Engineer
    Soles May 2007 - Sep 2007
    Guadalajara, Mexico Metropolitan Area
    I worked doing DFA studies to the Mechanical Assembly and be focused on reduction of parts and Stack Up tolerance analysis preventing components interferences.
  • Honeywell
    Mechanical Design Engineer
    Honeywell Sep 2006 - Sep 2007
    Mexicali, Baja California, Mexico
    I worked as a mechanical instrumentation Engineer designing instrumentation fixture for rakes and probes to be used during the Pressure and temperature Test engines.
  • Siemens
    Mechanical Development Engineer
    Siemens Jan 2005 - Dec 2006
    Tlaquepaque, Jalisco, Mexico
    I worked as a Lighting Engineer at “Auburn Hills” facility, in that period (two months) I did participate in a patent called: Compensation free illumination of instrument cluster display. Patent was released by the Patent US department; the patent number is: 7575331
  • Hp
    Research Development Mechanical Engineer
    Hp 2002 - 2005
    Guadalajara, Mexico Metropolitan Area
    &D Mechanical Engineer for Paper Handling devices doing the mechanical design of the Booklet maker and stapler stacker assembly. I got three patents released by the Patent US department, the patent number are: 6,827,346 called: “Method and apparatus for making booklets”. Patent number: 7,093,339 called: “Media fastening”. Patent number: 7,111,378 called: “Fastener closing”.
  • Hp
    Packaging Development Engineer
    Hp 2000 - 2002
    Guadalajara, Jalisco, Mexico
    started Packaging Engineering as a second skill. The plan was to have in the 2000 year the complete Packaging Engineering responsibility at the site. This activity includes the design.
  • Hp
    Safety Engineer
    Hp 2000 - 2002
    Guadalajara, Mexico Metropolitan Area
    I got the Safety and Regulations Engineer responsibilities focus on getting the international Safety and Regulation requirements like UL, CB, CSA and NOM.
  • Hp
    Quality Assurance Engineer
    Hp 1997 - 2000
    Guadalajara, Jalisco, Mexico
    As a Quality Engineer, I was responsible of Mechanical, Acoustic and Climatic Testing for all the Paper Handling Devices and set up a mechanical lab adding Acoustic laboratory capabilities at the site.
  • Lucent Technologies Bell Labs Innovations
    Research Development Mechanical Engineer
    Lucent Technologies Bell Labs Innovations 1994 - 1997
    Guadalajara, Mexico Metropolitan Area
    I worded as a mechanical engineer designing corded phone plastic housings like the135 Corded phone Telephone .My main contributions were: To finish the project 3 weeks ahead of the original schedule and a patent application called: “Reversible Base” which is a unique and complex design due the small space between the Lower Housing and the Base. US patent number is: 6,240,182.
  • Urrea: Tecnología Para Vivir El Agua
    Mechanical Design Engineer
    Urrea: Tecnología Para Vivir El Agua 1987 - 1994
    El Salto, Jalisco, Mexico
    I worked as a mechanical designer and product engineer of forja dies and tooling cuts for brass introducing the new forja products to the production line. I worked as a Tool Room and Design Department supervisor in charge of the design and tool fabrication managing eight Mechanical Technicians. My responsibilitieswere people management, forja dies production, heat treatment and the Tool Room Production Plan.

Francisco Ramirez Education Details

Frequently Asked Questions about Francisco Ramirez

What company does Francisco Ramirez work for?

Francisco Ramirez works for Intel Corporation

What is Francisco Ramirez's role at the current company?

Francisco Ramirez's current role is Engineering Manager.

What schools did Francisco Ramirez attend?

Francisco Ramirez attended Instituto Tecnologico De Monterrey, Centro De Enseñanza Técnica Industrial.

Who are Francisco Ramirez's colleagues?

Francisco Ramirez's colleagues are Heather Starr, Lauren Tippets, Chen-Yu Hsu, Wee Chek Heng, Susmitha Mohan, Rujuta Panvalkar, Ross Gilroy.

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