Frank Bennett Email & Phone Number

Fort Collins, CO, US

FORT Collins, Colorado, US

Built, setup LCD touch panel Digital Picture Frame Demo Application on Marvell - ARM SDK, develop board including build of u-boot, Linux kernel, drivers and user space. Evaluating speed / size of FPGA SOC, design tools:Xilinx ISE, Lattice ispLever Designed LCD, touchscreen expansion PCB for AVR32 based NGW100 board. Setup / Administer KuroBox, SOHO Network.

Indianapolis, IN, US

Developed Developed FPGA HDL, Verilog and Firmware for high speed data capture tester, based on ARM Cortex-A8, Spartan6, Ubuntu 14.04, Xilinx ISE 14.7 via TI's GPMC bus. FPGA HDL, Verilog and Firmware for high speed data capture tester, based on ARM Cortex-A8, Spartan6, Ubuntu 14.04, Xilinx ISE 14.7 via TI's GPMC bus.

Tokyo, JP

Brought up new Marvell ArmadaXP board design. Modified, built, debugged u-boot - marvell GbE SerDes port multiplexing, modified u-boot environment to bring up networking for ping, tftp. Configured, built, initramfs, kernel to boot linux - 3.2.27 for armada_xp. Setup developmenttools on Ubuntu and CentOS servers.

Redmond, Washington, US

Expanded Firmware functionality for new Touch Mouse product. Design involved 3 IDEs and 3 microprocessors: 6502 assembly, Cypress pSOC 'C', 'C#' test code and Nordic wireless dongle 8051 'C'. Coded and debugged ISRs, schedulers, SPI processor communication, RLE compression and packet formatting.

Palo Alto, CA, US

• Designed, tested Dual Pentium motherboard. Coded/tested firmware for 8051 System Maintenance controller, assembly language, ISR, BIOS support.
• Team member, block owner for four semi-custom ASIC design cycles. Designed, documented, wrote/tested 'C', Verilog RTL IP and verification code, synthesized and achieved 100 MHz timing budget for 2D/3D graphics pipeline.
• Microcode team member design, code and test of microcode for high performance i860 graphics workstation. Specifically coded, tested, integrated code for 3D matrix / transformation pipeline.

Rogerson Kratos – designed, delivered logic design, microcode and Assembler for LCD based EFIS avionics display processor.Mister Film - Designed floating point Math Engine with SCSI bus frame buffer for ray tracing. Unisys / USPS - Designed multi function card for IBM PC based workstation. Designed IBM/AT based floating point accelerator board based on NEC.

Architect of next generation product. Designed and tested raster calligraphic mixer for avionics applications. Performed hardware design using TTL, FAST, 10k ECL technologies for world's faster 3D floating point graphics processor, wrote firmware diagnostics, hardware design and wrote software tools in "C" computer graphic processors and digital display.

performed hardware modifications, design, test of the Frame Calculator subsystem of the Digital Image Generator(DIG), a real time, scanline computer, a frame buffer less raster visual flight simulator and supervision of 4 engineers. Own design increased the performance of number of polygon faces processed by 20%. The Face Processor is a vector pipeline.

Philadelphia, Pennsylvania, US

Lead Engineer - responsible for firmware structure and microprogramming of a special purpose graphics console based on a 16 bit amd2900 type processor. Supervised 3 engineers, the design and test of a prototype system and designed, coded and tested firmware 2-D vector clipping.Design Engineer - Designed worlds first, multi-micro master/slave PROM based.

Mee, Electrical And Electronics Engineering

Msee, Computer Architecture