Frank C. Xia Email & Phone Number

Austin, Texas, United States

Austin, Texas, United States

Responsibilities covered 2 generation (20 and 14nm tech nodes) production sustaining (high volume 300mm manufacturing) and process development on High Performance and Low Leakage CMOS Devices with FinFET, strained Si, high-k/metal gate• Owned 20/14nm FEOL Wet Etch/Wet Clean/Surface Preparation processes and equipment (DNS and SEMES single wafer), led teams to remove complex causes of sustaining issues, created new BKMs and specs• Initiated and executed projects; designed, executed, and analyzed advanced process experiments; drove understanding of root causes and optimized process conditions• Drove rapid continuous yield/defect/quality/process stability and capacity/reliability/cost/cycle improvements by working closely with Yield Enhancement, Integration, Research & Development, and Product Engineering teams • Managed project related matters, delegated or guided to complete technical efforts of junior engineers, engineering techs in a module• Provided technical leadership and reviewed technical directions of projects, emphasized critical issues and got engineers to take actions, made recommendations based on risks/rewards, and technical and business considerations• Expert understanding and expertise on semiconductor overall process flows, device structures and physics, defect and parametric data analyses, semiconductor surface and interface properties, wet clean chemistries and fundamentals.

Rio Rancho, Nm

Responsibilities covered 2 generation (45 and 32nm tech nodes) production sustaining (high volume manufacturing) and process development on High Performance and Low Leakage CMOS Devices with strained Si, high-k/metal gate• Owned 45/32nm FEOL wet etch/clean processes and equipment, led teams to remove complex causes of sustaining issues, created new BKMs and specs• Initiated and executed projects; designed, executed, and analyzed advanced process experiments; drove understanding of root causes and optimized process conditions• Drove rapid continuous yield/defect/quality/process stability and capacity/reliability/cost/cycle improvements by working closely with Yield Enhancement, Integration, Research & Development, and Product Engineering teams • Managed project related matters, delegated or guided to complete technical efforts of junior engineers, engineering techs in a module• Provided technical leadership and reviewed technical directions of projects, emphasized critical issues and got engineers to take actions, made recommendations based on risks/rewards, and technical and business considerations• Expert understanding and expertise in semiconductor overall process flows, device structures and physics, defect and parametric data analyses, semiconductor surface and interface properties, wet clean chemistries and fundamentals; received and passed 32nm seed engineer trainings on ~150 tech areas

Dallas/Fort Worth Area

Wet Etch/Clean/Surface Preparation Process Engineer, MTSResponsibilities covered 4 generation (130, 110, 90 and 65 nm tech nodes) process development and production sustaining on High Performance and Low Leakage CMOS Devices in Cu/low-k interconnect (dielectrics and metallization), STI, Gate and contact loops (oxidation, diffusion, thin film, etch, and clean processes)• Took principal responsibility for wet etch/clean, ash statistical process control (SPC) and defect reduction. Proactively uncovered multiple defect sources in the integration loop outside of process responsibilities. • Sustained and improved FEOL/BEOL wet etch, wet and dry clean processes, troubleshoot process/tool/yield/metrology/lot issues, wrote specs and established SPC, optimized process conditions to improve device yield, tool capability, cycle-time and cost • Led all aspects of new process developments for wet etch/wet cleans/surface preparation processes, include process selection, performance specifications, technical negotiation, process evaluation and improvement, and transfer to high volume production.• Established multiple new processes including:* SEZ wafer edge clean processes with controlled capillary flow and developed chemistry (eliminated 100% contact loop “hot dog” killer defects with 5.1% MPY improvement).* In-situ ash process for BEOL metal/dielectric loop integration with improved via and trench profiles (M1-M5 CD margin gain, reduced cycle time).• Initiated, executed R&D projects on post CMP clean, via/trench clean, defect reduction on Cu seed and ECD film, Cu surface passivation, edge peeling and polymer residue removing• Identified key issues on defect reduction and yield enhancement, designed and conducted experimental tests, extracted data from Spotfire, SMS, dataPower to analysis parametric and yield impacts of process change and process selection

Santa Clara, Ca

Responsibilities covered developing and implementing plasma etch solutions, tool startup, qualifications • Developed etch solutions for 130 nm tech node gate stack, STI and Cu/low-k Dual Damascene via/trench processes• Developed plasma metal and dielectric etch process platforms for key clients (Intel, TI, Agilent, IBM, Motorola) on Ferroelectronic RAM and Magnetic RAM devices, built up baselines for etch new materials (OSG, FSG, porous low-k, high k), tool matching, marathon and production release• Performed etch tool startups and process qualifications, managed problem accounts and provided tech directions• Diagnosed and resolved process, hardware and software issues on high temperature metal etch Centura, extracted process data to diagnose system downs, participated in customer meetings and troubleshot tech issues• Executed and analyzed experiments using DOE and ANOVA