Frank Chen Email & Phone Number

Hsinchu County/City, Taiwan

1. Post sale customer support.2. Pre sale customer engagement for Atrenta products.3. Customer training for Atrenta's products.

Taipei, Taiwan

Charge for customers in China and Taiwan SOC interconnect fabric support.Pre-Sale: Customers engagement to promote Sonics bus fabrics and memory performance IPs. It includes mock-up and evaluation.Post-Sales: Support customers adjust SOC bus fabric architecture (with Sonics bus fabric) to enhance performance and speed to meet customer system requirement.Analysis SOC performance and let bus & DDR work efficiency.Presentation Sonics products in IC-CAD and IIC of China.

Hsinchu, Taiwan

Engaged with customers and charge for three project execution and delivery.Project 1: ARM 11 base with Video, Audio, 3D (Mali), DDR II/III …etc. Gate count: ~8M. As Game machine Controller. (SIP) process: GF 65GProject 2: ARM 9 base with Video, Audio, and DDRII …etc.  Gate count: ~5M. As TPTV box Controller. (SIP) process: GF 65GProject 3: STB controller with DDR III. (SIP) process: GF 65G

Hsinchu, Taiwan

Charge for ARM base platform development, SOC chip spec. definition, Data flow analysis and chip testing.Progressing Project: ARM base platform 10M/100M Ethernet controller SOC chip with USB, PCI bus, and security engine for non-PC base internet access.Join Ethernet project for RTL coding, FPGA verification and whole chip verification. -> Mass production.USB3.0/USB2.0 Hub project spec. study and definition.

Shanghai City, China

Lead SOC-team, Completed 2 TD-SCDMA digital base band (3G/3.5G) IC design, Silicon first time success and on time Tape out. From System spec stage to volume production.Viking 2: 1500+ test pattern sets which passed on TI tester.Built up ASIC SOC group in Commit.Projects and Designs: 2 TD-SCDMA 3G DBB projects SUCCESS and 1 project to layout stageProject time Process Fab Spec1. Viking 2005/4Q 0.13um TSMC 3M GC + PLL2. Viking2 2007/2Q 90nm TI 8M GC + C55 DSP3. Viking3 2008/6 65/90nm TI Layout stage/Hold by company closed (3.5GHSDPA DBB > 9M GC)Viking/Viking2 are first time success and without ECO or Re-spin. Viking2 also made a real environment TD-SCDMA phone call in 5 days after ES chips return.First silicon success by 90nm for 3G TD-SCDMA/3.5G TD-HSDPA in WW/China and small volume production with NOKIA.Lower power implement with all chips.Test plan specification for wafer and manufacturing test for volume production at TI and TSMC.HandleViking2’s whole chip (c55 DSP insert) test plan and functional verification checklist.Characterization plan specification.Co-ordinate cross-teams, Including TI wireless/ TI San Diego/ TI Dallas / Wipro (India) and internal for feature define, system partition (SW/HW), data-flow-design, circuit design, verification, Signal-Integrity (SI), test circuit implement, test patterns development, roadmap planning, failure analysis and, Backend house emulation.

Taipei, Taiwan

Built up ASIC SOC TEAM in Princeton Technology.First silicon success by 0.18um for 8M Pixels DSC SOC Chip.Project Spec. definition & Schedule Handle (PM and project leader).Projects and Designs:8M pixels DSC controller with SIMD DSP structure project and 1 Core Technology Platform project for Multimedia.Project 1: Application: Using SIMD (Signal Instruction Multiple Data) structure 8 DSPs for Image processing. It also includes some peripherals to implement Multimedia Accelerator. (Scalar, MPEG encoder/decoder…etc.)Project 2: Core Technology Platform for Multimedia. It combines DSP and H/W accelerator to improve speed and reduce power consumption.

Taipei, Taiwan

Charge for ASIC/TI cDSP product Design and Application.As a project leader for many projects include processes : 0.55 um，0.35 um，0.25 um，0.18 um and 0.13 um…etc.Support ASIA customers in Korea/China/TaiwanIntroduce new TI flow to TI Korea ASIC team.Lead projects progress with customer design teams and Co-ordinate with TI Dallas ASIC support team.Experience of the entire design flow from chip structure analysis, data flow checking, floorplan, congestion check, P&R, test patterns generation, chip testing on TI tester, timing closure, simulation, verification, test implement. ...etc Projects and Designs: For over 10+ IC projects success to mass production, Key Projects are:Huawei: Line Card for Telecom Communication (China)OCI: 8 Channels E1 Mapper for SDH (China)Eastcom: SDH Switch Processor (China)Datong: 8 Channel E1 Mapper for SDH (China).MNWADC: SDH Router (China)Huawei: 19 M > 622M SDH Processor (Gate Count: 2.3M)ZTE: 622M to 622M Telecom Switch (Gate Count: 2.2M)Zyxel: Cable-Modem cDSP project (Taiwan).

Master'S Degree, Electrical And Electronics Engineering

Bachelor'S Degree, Electrical And Electronics Engineering