Application engineering:Root cause analysis and troubleshooting for HW and FW related issues about CPU peripherals and switch main board in data center field (e.g. DDR, SPI, I2C, PCIe LTSSM/AER...etc) during EVT, DVT and EVT phase.

Manage hardware LAB stuffs for ChromeBook at Google.

Data center switch HW design:-25.6T ToR switch design: Feasibility study, concept design with PI, SI , mechanical and thermal model. (e.g. 64 ports 400Gbps QDD, 2U, Innovium Teralynx-8)

Data center switch HW design.1. PI(power integrity) pre-sim and post-sim and measurement. 1.1 Using Cadence's "PowerDC" and "Optimize PI" to ensure the DC IR drop/AC PDN meets the requirement of whole system. 1.2 Power consumption/IR drop measurement.2. SI(signal integrity) pre-sim , post-sim and measurement. 2.1 Using Mentor Hyperlynx (Linesim / Boardsim) to simulate the low-middle signals of schematics circuit/layout topology , confirming the SI (signal integrity) will within SPEC with sufficient margin. 2.2 Cowork with SI peers to make sure the IL, RL, Crosstalk, TDR, BER of HSIO shall pass the SPEC (e.g. CtoC, CtoM). 2.3 SERDES confirmation/optimization by EYE oscilloscope measurement and/or FW commands.2.4 Analyst: e.g. Using protocol analyzer(e.g. Keysight PCIE(U4301B) Gen3 ) to identify if the system failure is caused by SoC/FW or board level related issues.3. PCB layout constraint and confirmation .4. HW Project lead: 4.1 Internal: Co-working with thermal, mechanical and SI colleagues to come up with a prototype that fit-in the requirement/SPEC from customer. 4.2 External: Interacting with vendors (e.g. PCB material/PCB manufacturer/High speed connector/Key IC), sourcing the proper combination for the system.5. HW schematics design, bring-up support, issue analysis and troubleshooting for data center switch .6. Customer support: e.g. Facebook on-site support (Menlo Park , CA) , short-term. e.g. Quanta (Server related project)

1.SoC/FPGA verification1.1 Flash(SPI-NOR/SPI-NAND/Parallel-NAND), DDR1/2/3 electrical validation and bootloader FW porting for memory controller.1.2 PCIE/USB signal compliance test.1.3 Peripheral I/O (Power/I2C/GPIO/UART/Timer...).1.4 Chip bring-up1.5 IC verificationValidating Logical/Protocol/Handshaking by using logic analyzer. (Instruction sets, data and behavior of specific IP).1.6 Preparing IC layout guide.1.7 Co-work with digital/analog IC designer during FPGA/ASIC verification cycle.2. FPGA, QA board design/manufacturing for IC verification purpose.3. SI:Using Cadence "PowerSI" to check HSIO's TDR and x'talk.4. Validating if FPGA/ASIC waveform matches with IC designer's RTL design and/or simulation in aspect of logical and performance, preventing possible RTL design error happens.5. IC Spec definition about memory.6.Involving IC verification from FPGA till MP stage.7.Customer support for IC HW issue. e.g. Huawei on-site support (Beijing/Shenzhen) directly, short-term. e.g. Assist FAE to solve issues from customers, indirectly support.