Systems and Technology Group Package electrical rule checking development and test; Vector network analyzer measurements on glass ceramic packages; HFSS modeling of package structures; Signal integrity and power network analysis of organic packages;

Evaluated circuits in the Phase Locked Loop (PLL) for future microprocessor product for the Sony Playstation* III platform. Designed PLL loop filter leakage correction circuit. Performed transmission line characterization for high-speed package design.

Synthesis Place and Route Group R&D2001 Tested and quantified benefits of Cadence's crosstalk prevention CAD capabilities on 0.25 and 0.18um benchmark circuits. Hands on experience with Cadence's Synthesis Place and Route tool suite (PKS, Buildgates, QuickPlace, Wroute, HyperExtract, CeltIC). Developed tool guidelines for crosstalk reduction and made recommendations on future studies based on simulation data.

Itanium* Processor: LP domino library standard cells, functional unit block in L0 cache for low power, clock distribution network analysis and design; datapath circuit analysis (performance/power/area tradeoff for primitives); Quantified effects of retiming in Itanium* circuits; CAD Projects: Verilog XL & PowerMill Power Estimation Tools (Pentium II*): Programmed Verilog UDPs; Performed library conversion and maintenance; Wrote scripts and supported tool users; Tested and correlated power tools for increased accuracy. RTL Power Estimation Tool (Pentium IV*): Tested power models for datapath megacell circuits; Built library of datapath primitives; Validated RTL memory power model; AMPS transistor sizing optimization: Tested tool on various circuits and deployed to internal design teams.Design Advisor Tool Development: Tested novel CAD tool for datapath design and automated layout for Intel's future server processors.

Q & R Development Tools and Flash Memory Group Performed characterization of probe holes aspect ratios for C4 packaging technology; Evaluated 3D reconstruction software tool for use with a confocal microscope; Performed finite element stress modeling (ANSYS) on via structures as a function of temperature. Tested flash memory mini-arrays for project involving placement of two bits of information per flash unit. Wafer level test and characterization of reliability in flash memory cells.