15+ years semiconductor experience in TSMC include: 10+ years of R&D experience for 2.5D/3D IC package in CoWoS-S4+ years of 80nm/45nm/40nm CMOS process integration 1+ year(recent) NPI experience for InFO_LSI substrate applied in 3DIC package
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Principal EngineerTsmc Oct 2020 - PresentHsinchu City, Taiwan, TaiwanSpecial Turnkey Program, Advanced Packaging Technology and Service (NPI)Principal Engineer- InFO LSI Substrate (70mmX70mm) NPI for company-A: Yield significantly raised up and migrated to high volume manufacture (4k/month)- New substrate fab bring-up and successfully met mass production schedule- Substrate supplier (Korea and Japan) bring-up: cross supplier NPI experience to fasten the bring-up schedule- Customer returns verification: substrate defect escaping prevention, and guide supplier for failure analysis- Cross team (substrate supplier, BU, CE, in-house OSAT and QA) cooperation: Ensured NPI schedule, suppy plan, and qualification plan for recent mass production -
Principal EngineerTsmc Aug 2016 - Oct 2020Hsinchu, TaiwanTSV Integration Program, Integrated interconnect & Package DivisionCoWoS process research and development, product management, transition to mass production- Qualified Gen-1 ~ Gen-2 CoWoS-S package process with compliant JEDEC standard, and demonstrated significant assembly yield for Gen-3 CoWoS-S- Expanded CoWoS-S technology envelop: demonstrated integration of homogeneous, heterogeneous FPGA, and SoC with 3rd party HBM die.- Extended package size from 45mmX45mm to 70mmX70mm: introduced and verified reliability for adhesive, lid/ring surface treatment, substrate core material - Extended the interposer size from 1X reticle (800mm2) to 2X reticle (1600mm2): introduced CoW and oS underfill, and broke through interposer size by stitching masks - Increased C4 bump counts from 15k to 80k: introduced and verified reliability for oval Cu bump, coordinate compensation, and bump size control for C4 joint ability - Increased uBump counts from 350k to 1000k: introduced and verified reliability for multiple pitch and structure ubump, and broke through joint ability by joint condition -
Senior Integration EngineerTsmc Aug 2010 - Jul 2016Hsinchu, TaiwanTSV Integration Program, Integrated Interconnect & Packaging DivisionCoWoS process research and development, product management, transition to mass production
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Integration EngineerTsmc Aug 2006 - Aug 2010Hsinchu City, Taiwan, TaiwanFab12 Nano Tech. Integration IV Department- N45/N40 CMOS integration for product ramp-up: support to qualify N40 interconnect reliability, successfully ramped up to 200pcs/month with yield >98% for N40 product- N80 product sponsor for 8,000pcs/Quarter of GPU wafers, taped out and delivered ~40K pcs wafer of GPU chips -
Assistant EngineerShinkong Synthetic Fibers Corporation Jan 2001 - Jan 2004
Franklin Fish Skills
Franklin Fish Education Details
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Department Of Chemical Engineering -
Department Of Chemical Engineering
Frequently Asked Questions about Franklin Fish
What company does Franklin Fish work for?
Franklin Fish works for Tsmc
What is Franklin Fish's role at the current company?
Franklin Fish's current role is Principal Engineer at TSMC.
What schools did Franklin Fish attend?
Franklin Fish attended National Tsing Hua University, National Taiwan University Of Science And Technology.
What skills is Franklin Fish known for?
Franklin Fish has skills like Reliability, Keyence Laser Scanning Microscopes, Zeiss 3d X Ray, Research And Development, 半導體, Semiconductor Industry, Process Engineering, Research, 積體電路, Substrate, 2.5d Ic Package, Failure Analysis.
Who are Franklin Fish's colleagues?
Franklin Fish's colleagues are Jun-Pu Chen, Wei-Jen Chou, Rong-Cun Pan, 江昱儒, Emelyn Chien, Ah Emran, Yawlin Hwang.
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