Fred Session Email & Phone Number

Responsible for managing all conductor etch projects for DRAM,3D NAND and emerging memory technologies at Micron Fab 4. Managing on-site head-to-head activities for P&D of new technology nodes. Evaluating new chamber hardware and processes. Coordinating productivity efforts across multiple sites. Work with customer and Lam technologists to map out process flows using Coventor 3D simulation to help speed up cycles of learning.

Responsible for all deposition and etch process support at Micron Fab 2 Processes/ Equipment and Customer supported: • TEOS/ TEOS xT • AHM Carbon/ Vector Extreme • CVD W/ Altus • ALD WN/ Altus Max Fill • ALD/ Oxide and Trim-Dep applications • Kiyo chambers Site technical lead for TEOS productivity HtH which was won by Lam. Site technical lead for ALD oxide liner and Trim-Dep eval which resulted in a 5-triple chamber platform purchase. Technical lead for all tool installs and Beta-site evaluations. CIP and Productivity improvement projects.

Process Development Manager (2010 –present):Manage all front-end Si development including Etch, CMP, Photo, Diffusion, Thin films and Epi.Manage process development resources for all new product development.Manage major feasibility projects for cost reduction, process simplification, parametric variation reduction, new equipment evaluations and enabling technologies. In charge of process transfers for new and existing technologies to foundries and internal factories. Principle Engineer (2003 – 2010): Head of etch and CMP process development group.Responsible for evaluation and development of new etch and CMP processes, to support bringing new products to market. Including cost and feasibility and risk analysis, yield improvement, parametric variation reduction and determining process capability and manufacturability.Evaluation of new etch, CMP and metrology systems to meet the needs of the next generation products.Managing the development efforts and projects of process development group comprised both etch and CMP. Designated Key Technologist within Fairchild Semiconductor Corp. Awarded Patent of the year for the method of fabricating an in-trench interpoly dielectric layer.

Staff Engineer (1996 to 2003): Supported Lam semiconductor capital equipment manufacturing at customer locations in North America and Europe.Responsible for the development and characterization of plasma etch processes and hardware. The bulk of my work has been with both medium and high-density plasma etch systems used in metal, silicon (gate and trench etch) and dielectric etch applications. This includes critical gate, shallow and deep trench isolation etches, high aspect ratio contact and via and various low k materials as well as various metallization schemes and complex metal gate stacks. Worked closely with the factory on product improvement, beta-site testing, hardware development and advanced customer applications. I also served as one of the regional technologist where I worked on aligning the customer and factory technology road maps and help solve customer’s integration issues. Regional Process Manager (8/99 to 11/99): Western Region Field Process group Engineering Manager where I supervised the projects and resources for multiple internal and external customers within the region. Reviewed and negotiated equipment purchase specs and managed manpower requirements. Senior Process Engineer (1994-1996): Supported Lam semiconductor capital manufacturing equipment at customer locations in North America.Responsible for new equipment installations at multiple customer sites.Acted as intermediate between customer and factory.Worked on multiple cross-functional teams with customers to solve process and integration issues.

Process Engineer at Carlsbad Tech. Center.Senior Process Engineer: Supported dry Etch, PVD (physical vapor deposition), Ion implantation and CVD (chemical vapor deposition) areas in a research and development environment.Responsible for process development, integration and sustaining of multiple product lines. Worked on a wide range of CMOS and BiCMOS technology development efforts for Silicon on Insulator (SOI), SiGe and GaAs devices. Worked on multiple projects from inception to final integration including device design, process flow and development as well as analyzing electrical and physical test data. Responsible for failure analysis utilizing a number of analytical techniques.