Frederic Roger Email & Phone Number

Cupertino, California, Us

Top Down Design, Automation, Processes, Methodology, simulator, software

Cupertino, California, Us

•Cross-functional chip leadership spanning all Analog and Mixed signal IPs for Apple’s SOCs•Drive early and ongoing alignment with cross-functional teams•Drive silicon roadmap in collaboration with Technical Engineering•Manage vendor relationship and drive silicon execution•Report status at VP and SVP level•Introduction of tools and processes for scalability and efficiency of engineering

•In charge of developing multi-million sensor array SOCs for our next-generation DNA sequencer•Architecture and development of the Software stack: hardware drivers, DNA sequencing application layer, cloud analysis pipeline•Hands on involvement in all development phases: strategic planning, project management, chip lead, design, silicon and instrument test and characterization, Python drivers’ development, integration in the DNA sequencer, FPGA development

Sunnyvale, Ca, Us

• Technical lead and management of all analog and RFIC activities• In charge of the test development for ATE and bench• Analog architect of SC1887, SC1889, SC1894, SC2200: analog predistortion ICs for Power Amplifiers.- Development and implementation of the full custom CAD flow: PDK integration, Pcells development, tools installation...• Design, layout and bring up of various RF and mixed-signal block such as:----- novel analog processing engine: generation of analog polynomials for analog signal processing----- novel RF power detector----- novel True RMS power detector for absolute RF power measurement----- LO generation----- 12 bits integrating ADC----- Current steering DACs

De

• 5 years of IC-Design management. Report to the CEO. • Chips developed- XT53 Family: Silicon Timing Solutions for SONET/SDH applications- XFI transceiver- 10Gb/s SERDES for SONET applications- Dual channel VDSL analog front end• Design, layout, silicon bring up of multiple mixed-signal circuits going from low speed high linearity circuits up to 10Gb/s:LC VCO, CMU, charge pump, quantizer for continous-time sigma delta ADC, 10Gbits/s multiplexer, pre-emphasis,... • CAD activities:- Programming of advanced Pcells in Cadence SKILL language. - Development of tools for layout and design acceleration in the Cadence framework- Preparation of PDK for customers.

Neubiberg, München, De

Design and layout of various mixed-signal circuits for Gold Baseband family in 0.13um, 0.18um and 0.25um IFX/IBM CMOS technologies.Focused on low power, high yield designs for high volume mass products.Main contributions:• Hi-Fi DAC for the voice band• Low power (5mW) sigma delta ADC for UMTS • 10 bits 50MHz DAC for UMTS • Project lead for E-Gold V4 analog macro

Design of high-speed electronics for particle physics experiments. (Chooz and Borexino).Main contributions:• Design, layout and test of a 3 channels 400MHz acquisition VME board for the Borexino physics experiment.• Test and installation of an 8 channels / 200MHz Fastbus acquisition board in ECL logic for the Chooz experiment dedicated on the research of neutrinos.