G Senthil Kumar Er Email & Phone Number

Bengaluru, Karnataka, India

Working with RISC-V Core

Chennai, Tamil Nadu, India

Gaining working skills in System Verilog/UVM with AXI , AHB & APB Protocol, AXI & APB VIP, AHB UVC Development, Ethernet Switch and Memory Controller/DMA Controller Verification. UVM: UVC development for AHB & APB protocols and functional verification using SV & UVM of AHB Interconnect. Register model development for USB Core. USB4 Protocol Learning covering: #USB Protocol, Link, Physical layers #Design implementation for all layers #Testbench component coding for all layers.

Loyola College Campus, Nungambakkam, Chennai

🌟🌟Was Awarded Best Teacher in the Formation of Students🌟🌟 IITM, Research Park, MedTek Incubator, Partnership & Mentor for a Startup of all girls team from LICET 🌟🌟 Principal Investigator for an Industrial - Institute Collaboration project - WeGot Utility Solutions, Channai🌟🌟Experimenting new methods of teaching-learning processForming project groups for VLSI EngineersWorking as team with students to execute socially relevant projects

Erode Area, India

Erode Area, India

Tircuhengode, Nammakkal, Tamil Nadu

🌟🌟Was Awarded for Excellence of Contribution with Placement Team & 100% Percent Result🌟🌟Foremost duty to Teach students fundamental concepts in VLSI/Electronics and CommunicationAs Placement Training Co-Ordinator/ECE to trainee students for better job opportunitiesAs Class Ad-visor take care of students needsAs Website Co-ordinator/ECE to maintain and improve content and reach of the Dept. website - NBA Standard

Rsm Nagar, Gummidipoondi Taluk, Puduvoyal, Thiruvallur, Tamil Nadu 601206

Started my Teaching Career here, transformation: Industry Professional to Academia

Hcl Tech, Amb-4

Live Project, Project trainee (5 months Jan 2007 to May 2007) worked on SATA Link Layer Design.As MTS i was given opportunity to work on Aerospace projects.I am entrusted to verify designs of FPGAs used in Aerospace Industry

Ambattur, Tamil Nadu, India

🌟🌟Got Star performance from client end for capturing bug in spec and was well rewarded.🌟🌟Worked in Front End Verification Projects, 1. responsible to write testcases - corner cases & sanity cases adhering to DO-254 standards. 2. Held moderate level ownership of testbench environment.

Vlsi Chip Design Verification Engineer, Semiconductor Manufacturing Technology

Gaining working skills in System Verilog/UVM with AXI , AHB & APB Protocol, AXI & APB VIP, AHB UVC Development, Ethernet Switch and Memory.

Doctor Of Philosophy (Phd), Vlsi Testing, Pursuing

Activities and Societies: Test Data Compression and De-Compression, Test Vector Re-ordering, Low Power TestingPower aware compression.

Master Of Engineering (Meng), Vlsi Design, First Class

Activities and Societies: Vice-Chairman: IEEE Student Chapter @ KECE, ISTE Member

Bachelor Of Engineering - Be, Electrical, Electronics And Communications Engineering, First Class

Activities and Societies: SAANKATIKA’04: QUIZ COORDINATOR in ECE Department SymposiumStudied BE ECE

Early Schooling

Schooling

Education record