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Gabriel Thompson Email & Phone Number

Senior Research and Development Engineer at fJscaler at fJscaler
Location: Portland, Oregon, United States 10 work roles 2 schools
1 work email found @luminous.com LinkedIn matched
✓ Verified July 2026 4 data sources Profile completeness 100%

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Work email g****@luminous.com
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Current company
Role
Senior Research and Development Engineer at fJscaler
Location
Portland, Oregon, United States

Who is Gabriel Thompson? Overview

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Quick answer

Gabriel Thompson is listed as Senior Research and Development Engineer at fJscaler at fJscaler, based in Portland, Oregon, United States. AeroLeads shows a work email signal at luminous.com and a matched LinkedIn profile for Gabriel Thompson.

Gabriel Thompson previously worked as Senior Research And Development Engineer at Fjscaler and Staff Mixed-Signal Design Engineer at Luminous Computing. Gabriel Thompson holds Master'S (Thesis), Electrical Engineering from Purdue University.

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Email format at fJscaler

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{first_initial}{last}@luminous.com
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Profile bio

About Gabriel Thompson

I am currently a full-time employee at Luminous Computing working on next-gen IC design for optics and AI specific hardware.Skills:Silicon Debug: High-speed oscilloscopes, BERTs, power amplifiers, duplexers, spectrum analyzers, power sensors, VNAs, active loads, etcSoftware: Python, C, Bash, Cshell, Cadence, Spectre, Matlab, Hspice, Microsoft Office Suite, JMPDesign Skills: Low-noise amplifiers, mixers, voltage regulators, high-speed transmitters (Tx), high-speed receivers (Rx), digital PLLs, clocking integration, DLLs, RFIC

Listed skills include Analog Circuit Design, Rf, Debugging, Pcb Design, and 3 others.

Current workplace

Gabriel Thompson's current company

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fJscaler
Fjscaler
Senior Research and Development Engineer at fJscaler
AeroLeads page
10 roles

Gabriel Thompson work experience

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Senior Research And Development Engineer

Current

Analog/Mixed signal circuit designerAnalog/Mixed signal tool developerPost-Si circuit debug leadDesign <-> Verification communication lead

Jun 2023 - Present

Staff Mixed-Signal Design Engineer

Mountain View, California, Us

Post-Si Testing Infrastructure: Building on previous projects, created a complete analog debugging and characterization suite using Python. The top-level script can automatically scale power supplies, interface with instruments, read/write registers on silicon, and record test data with ease.Automated Layout: Using the Berkeley Analog Generator (BAG), quickly created a completely configurable power grid implementation including bumps, ESD, and ports to other IPs on the chip. This project used Python to integrate to cadence to create the designs amazingly fast. Designed a script that runs all of the flows in an automated way (DRC, LVS, Extraction) to further speed up TTM for the BAG and the rest of the team.High-Speed Passive Front-End: Designed a front-end for a 28GHz interface on an SOI process, including an Rterm circuit, ESD, and a Tcoil to help improve bandwidthESD: Responsible for all ESD on the chip, including designing custom clamps, verifying digital/standard ESD solutions provided by the foundry, and planning for all power clamps/devicesSPI Implementation: Designed a complex state machine interacting with multiple clock domains in System Verilog and verified the design with a complex yet nimble System Verilog testbench

Nov 2021 - May 2023

Senior Analog Ic Design Engineer

Santa Clara, California, Us

DDR PHY: Designed and implemented several critical circuits, including analog Rx timing circuits, slow-speed Rx, custom powergates and other power-saving circuits. Also owned the overall Rx timing architecture. Oversaw several project-wide integration efforts such as including analog routing review, crosstalk analysis, and power grid simulation.LPC Aging PRT: Lead engineer for a critical customer-facing issue affecting a broad range of SoC designs, providing a constant stream of critical simulation data to customer representatives/press release teams, diagnosed the extent of the issue, came up with multiple solutions in a short time frame to limit the company’s further exposure.LPC/SDCard Front-end: Owned, designed, implemented, integrated, and tested a 200MHz high-voltage transceiver, including a novel distributed ESD methodology (patent pending)

Mar 2015 - Oct 2021

Analog Ic Design Engineer

Santa Clara, California, Us

Post-Si Debug: Designed and coded a complete hardware testing software infrastructure for the Haswell processor family’s DDR IP, increasing debug speed by a factor of 10. Aided its implementation on-site in Penang, Malaysia. Implemented this same solution, driving IO characterization for the Broadwell, Apollo Lake and Broxton/Broxton-P processor families as well.Digital Clocks: Designed an ultra-low-power 400MHz digital PLL in 14nm CMOS, providing a precise clock for downstream GHZ PLLs to use as their reference

May 2011 - Mar 2015

Systems Engineering Intern

Santa Clara, California, Us

FTDI Project: Designed hardware/software package to quickly debug and program platformsPlatform Debug: Contributed to two different Power-Ons, quickly debugging systems, saving Intel $100,000s by fixing broken test platforms

Aug 2010 - May 2011

Teaching Assistant

West Lafayette, In, Us

Taught two lab sections, two "DPS" (Directed Problem Solving) sections, and holding three hours of office hours per week for the course ECE270. This is a basic course on digital system design.During the summer, I was promoted to "Course Instructor" for ECE202, "Linear Circuit Analysis II". This is Purdue's second circuit theory class which covers s-domain analysis, convolution, transformers, and two-port circuits. As Course Instructor, I was in charge of preparing and presenting lectures, writing and grading exams, and assisting students whenever necessary.In the Spring of 2010, I was honored as a recipient of both the Magoon award for TA excellence and the CETA teaching award. Both are only given to a select few students, and to have both honors speaks to my communication ability and understanding of the coursework.

Aug 2008 - May 2010

Electrical Engineering Intern

Olathe, Ks, Us

Fishfinder Project: Worked on fishfinders 300c and 400c, re-designing the power supply to use a cheaper, better supply and provide more output power to the transducer

May 2008 - Aug 2008

Part-Time Electrical Engineering Intern

Manhattan, Kansas, Us

KDOT Rebar Sensor: Designed rebar sensor for KDOT to detect correct construction of roadsMisc Debug: Debugged and fixed a $100,000+ milling machine at no cost. Tested a solar-powered wait-time sensor for KDOT

Sep 2007 - May 2008

Electrical Engineering Intern

Olathe, Ks, Us

Wireless Hub: Designed the schematics and PCB for a prototype wireless dongle that interfaced with all Garmin’s marine sensors, greatly simplifying boat/yacht wiring systems

May 2007 - Aug 2007

Electrical Engineering

S And Y Industries

For the first half of this internship, I acquired valuable hands-on experience and intimate knowledge by building products and soldering different components. For the second half of the internship, I worked in the QC department where I tested the final products and troubleshot the broken circuits. In this arena, I developed my basic logical troubleshooting skills that are still with me today.

May 2006 - Aug 2006
2 education records

Gabriel Thompson education

Master'S (Thesis), Electrical Engineering

Purdue University

Bs, Electrical Engineering

Kansas State University
FAQ

Frequently asked questions about Gabriel Thompson

Quick answers generated from the profile data available on this page.

What company does Gabriel Thompson work for?

Gabriel Thompson works for fJscaler.

What is Gabriel Thompson's role at fJscaler?

Gabriel Thompson is listed as Senior Research and Development Engineer at fJscaler at fJscaler.

What is Gabriel Thompson's email address?

AeroLeads has found 1 work email signal at @luminous.com for Gabriel Thompson at fJscaler.

Where is Gabriel Thompson based?

Gabriel Thompson is based in Portland, Oregon, United States while working with fJscaler.

What companies has Gabriel Thompson worked for?

Gabriel Thompson has worked for Fjscaler, Luminous Computing, Intel Corporation, Purdue University, and Garmin International.

How can I contact Gabriel Thompson?

You can use AeroLeads to view verified contact signals for Gabriel Thompson at fJscaler, including work email, phone, and LinkedIn data when available.

What schools did Gabriel Thompson attend?

Gabriel Thompson holds Master'S (Thesis), Electrical Engineering from Purdue University.

What skills is Gabriel Thompson known for?

Gabriel Thompson is listed with skills including Analog Circuit Design, Rf, Debugging, Pcb Design, Analog, Ic, and Fpga.

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