Gagandeep Singh Matharoo Email & Phone Number

York, England, United Kingdom

• Worked in the York Plasma Institute for the design and characterization of Pulsed Power Generators for plasma-activated water generation.• Designed a solid-state Marx Generator with flexible characteristics such as amplitude and repetition rate.• Characterized the pulsed atmospheric pressure plasma with UV-Vis and Optical Emission Spectroscopy. • Comparing the Plasma process and Electro-Fenton process for the degradation of sulfamethoxazole in water.

Liverpool, England, United Kingdom

• Worked in the Electrical Engineering department for the design and characterization of Pulsed Power Generators for plasma-activated water generation.• Designed a solid-state Marx Generator with flexible characteristics such as amplitude and repetition rate.• Characterized the pulsed atmospheric pressure plasma with UV-Vis and Optical Emission Spectroscopy. • Comparing the Plasma process and Electro-Fenton process for the degradation of sulfamethoxazole in water.

Munich Area, Germany

Implemented a study on Dip-coating versus Spin-coating as different methods for forming Self-Assembled Monolayers on Titanium Nitride, reducing the required time by 100-fold.

Munich Area, Germany

• Worked in the Vehicle Networks team for the simulation and verification of automotive CAN-FD Networks. • Designed the Verification flow for Signal Integrity reducing the measurement time of width and ringing in Analog waveforms.• Documentation of results and preparation of presentation for the customer.

Bengaluru Area, India

• Worked in the Analog Design team for the development of automated Design flows. • Completed the automation of Voltagestorm flow for IR drop analysis using Cadence Voltus.• Developed a Perl Script to run all Validation checks on Hard IPs reducing the validation time to one-tenth.• Coordination with Digital and Verification teams for the implementation of Design flows in the Analog team.

Noida Area, India

• Worked in the CAD team for the generation of Timing models for Digital Hard IP’s using Synopsys PrimeTime.• Developed a Perl script to extract the timing values of tri USBPHY from a single USBPHY helping to reduce the overall processing time to one-third.• Providing feedback to the tool designer for possible improvements in the ST Validation tool.• Initiated weekly Conceptual learning lessons regarding Timing analysis and Synopsys PrimeTime.

Noida Area, India

• Worked in the Layout Design team for the development and improvement of IO and Analog Layouts using Cadence Virtuoso. • Responsible for the reduction in the width of the IO block from 180um to 150um saving 120um space on the Chip.• Generation of DRC and LVS clean layout design using Mentor Calibre.

Master’S Degree, Communications Engineering

Exchange Semester, Electrical Engineering

Bachelor’S Degree, Electronics And Communication Engineering