- Having 23+ years of experience in IP, ASIC and SoC verification with prestigious semiconductor companies (NitAl, QLogic, OpenSilicon, rENIAC, Marvell and Intel)- Experience in verifying designs at system and block level- Experience in VHDL, Verilog, Vera and System Verilog based verification- Experience in verification with methodologies like VMM and UVM- Strong background in Networking protocols. Worked on Ethernet(10G and 100G), TCP/IP, Infiniband, I2C, SMBus.- Experience in functional verification of TCP/IP offload (TOE) engines using UVM.- Experience in Behavioural modelling - Working knowledge of shell and Perl scripting.* Specialities:- Develop re-usable UVM Verification IPs or UVM Verification Components (UVC) for different interfaces to be used at different abstraction levels of verification.- Effective use of UVM features to build Verification architecture and methodology.- Verification project planning and execution to aid Design Cycle.- Set processes for Verification automation to speed-up project execution and effective utilization of engineering resources- Ability to manage, motivate and get the best performance from team and individuals.