Ganesh Murthy Email & Phone Number

Sacramento, Ca, Us

Redmond, Washington, Us

Santa Clara, California, Us

• Drove Intel’s flagship CPUs into several OEM/ODM DT, HEDT and Gaming designs. Hand hold OEM/ODMs through product life cycle: delivering CPU ES/QS/Prod samples, helping with customer board design reviews, supporting customer sightings. Worked closely with Intel and customer top level managements, cross geo functional teams throughout the product launch cycle resolving several launch gating issues. Responsible for the successful launch of Intel Ci9 12900K series of “Best Performing DT” and Intel Ci9 10900X “Best Gaming experience in the world” HEDT systems. • Manage an Overclocking workshop every year. In this event, various internal teams - BIOS, DDR, CPU HW, Microcode, Clocking, Thermal, Validation experts are pulled together to help OEM/ODMs realize their CPU and memory overclocking goals. Facilitated Extreme Overclocking where customer use Liquid Nitrogen to create overclocking world records. Delivered a stunning “greater than 7Ghz” overclocked 16 core 12900K – a world record in DT CPUs.• Oversaw the adoption of DDR5 on 12900K series CPU. Drove special workshops that helped resolve several DDR5 margining issues, worked closely with Memory supplier to make sure DDR5 4800 MT/s in Mass Production aligned to Intel CPU launch schedule. This led to the first industry wide adoption of DDR5 starting with Intel 12900K CPU.• Organized PCIe Gen5 workshop to ensure OEM/ODM designs capable of supporting PCIe Gen5 devices. Given no PCIe Gen5 devices available to test with, a solid enabling plan including a workshop for PCIe Gen5 compatibility was developed and executed. This proposal helped Intel and our customers be ready for PCIe Gen5 devices as they have started becoming available late 2021 and early 2022.

Santa Clara, California, Us

Ownership of DRAM decisions on Intel’s tablet products. From a power, performance, cost and form factor perspective, recommended the appropriate DRAM intercept to each platform. Key accomplishments:• Introduction of the 253b LPDDR3 package into an Intel ATOM SOC. This allowed us to use two LP3 packages instead of the standard four LP3 packages. The reduction in memory footprint allowed us to fit into a smaller motherboard thereby enabling larger battery. This effort enabled Intel to come up with a cost effective tablet solution with similar battery life compared to the iPAD3.• Performed detailed memory power analysis to identify best of class DRAM devices in Intel phone and tablet roadmaps. Enabled Intel to drive 2 separate tablet SKUs – the performance SKU that used LPDDR3 and the Value SKU which was a sub $400 tablet using DDR3L.• Developed a proof of concept design to showcase a single 64b channel DDR3L implementation that paved a path for OEMs (Dell, ASUS, Lenovo) to support both a 2GB and a 4GB memory sub system without need for 2 separate board implementations.

Santa Clara, California, Us

Worked on DDR3, GDDR5 and Thermal Sensor for Sandybridge, Ivybridge based PC platforms. Key accomplishments in this role:• Proposed addition of DDR3L memory support on IVB processor based upon OEM/ODM requests. Worked with the design team to show the benefits of DDR3L in terms of pricing, power benefits, and the expected MSS loss we would have had given the comp was supporting DDR3L. After a significant effort, the CPU design team accepted my recommendation and added DDR3L support to their CPU. • Worked closely with 4 external vendors to identify the best possible thermal sensor needed for the Penryn processor. Because of the dedicated work engaging with vendors, Intel was able to successfully launch Penryn processor right on schedule.

Santa Clara, California, Us

Supervised Static Timing Analysis on Intel’s Flagship Desktop chipsets. Owned clock and clock crossing collaterals, delievered 4 Desktop Memory Controller products with “0 Setup/Hold violations”. Some of the key accomplishments in this role: • Designed and implemented “Margin Meter” circuits that enabled us to get an accurate representation of setup/hold margin across different die locations. This process helped me fine tune the setup/hold uncertainities we used during the presilicon process and led to better yields.• Managed a Presilicon Validation Team (4 engineers) for an Intel chipset over a period of 2 years. The validation team developed BFMs trackers and checkers using advanced VHDL constructs for an internal chipset bus. • Design Manager for 2 steppings of this product and worked closely with cross Geo and cross Functional teams in Folsom, Dupont and Penang coordinating all activities and saw these steppings through tapeout.

Santa Clara, California, Us

Worked on several aspects of chip and interface design – Video conferencing chipset design, fault grading, 1394 and USB. Some key accomplishments in this role: • Developed industry standard compliance checklist for P1394.a spec and drove compliance of PHY/Link silicon with major partners like IBM, TI, SGS and Phoenix technologies.• Developed 2 pass Scan methodology, achieved 95% coverage on two ASICS.• Patented a Multi Play Protocol which has Integrated Softset, Plug and Play and fixed boot. All design entry in VHDL, FUB level Simulations under V-Systems in Windows and QuickVHDL in Mentor Unix environment.

Ms, Engineering

B Engg, Electronics And Communications

Education record

Education record