Planned, executed, and debugged OOP testbench code, sequences, and models to guarantee RTL or FW implementation met specifications for server chipsets. Focused on delivering first-time functional IP blocks to full-chip integration for an array of chips. Achieved expert status in significant aspect of each validation project encountered.* A key factor in success of microserver project. A major contributor towards enabling a blockbuster early PRQ due to high stability of SDRAM controller exhibiting no blocking issues. * Work on Power Management Controller enabled meeting A0 tape-in on schedule. Quality of work contributed to achieving A0 silicon power-on exit of PCH without a single FW bug patch, which is extremely rare in a major platform A0 power-on. * Employed expertise to expose corner case conditions that could be probed in search of suspect logic. Strove to cover these areas through test expansions, custom randomized test generators, and modeling of interfacing logic. Isolated failure in current DMA IP hidden through four years of real-time use of predecessor in field.* Ability to debug issues autonomously deep into RTL highly regarded by peers. Independently drives to foundational logic understanding to ensure correct bug fix.Owned both RTL-coding and validation of modules displaying cross-discipline abilities.* Coded fetch block for message unit prototyped in FPGA; met short project schedule.* Coded power state message flows, thermal throttling, and enhanced lock arbiter in switch arbitration logic of integrated IO module. Documented uArch specifications.

Validated functionality of Calibre xRC parasitic extraction tool to ensure product quality.* Created and debugged tests for new functionality from specifications in support of 8 SW developers. Released tests to regression suite once repeatable.* Managed test regression suite.* Produced quarterly releases consisting of legacy code combined with new functionality.* Produced customer-driven patch releases on more frequent schedule throughout each quarter.* Liaison for test-related issues for the xRC group.* Wrote Perl scripts for test automation and regression maintenance.

Developed C code for remote monitor/control system for startup in radio industry.* Built engine behind touch-screen user interface.* Enabled user control of data capture and subsequent flow over TCP-IP.

Developed integrated circuits for end-products in the consumer market. Planned, executed, and debugged verification tests for multiple projects at block and system levels to ensure chip functionality and timing.* Possesses coding skills critical to chip development. Utilized them to develop C and Perl models for image processor block-level and top-level verification.* Created system-level camera module simulation which became verification methodology standard in imaging lab.* Guaranteed functionality of 3 generations of digital still camera chips. Automated environment to enable around-the-clock test generation driving ever lower bug rate.Led verification team for Multi-Function Peripheral SoC.* Background relied on to identify/allocate tasks, advise in project planning.* Point-source supported mixed-language simulation environment enabling 16-engineer SoC team to guarantee first-time correct silicon.RTL-coded block designs from specification for CMOS imaging ASICs.* Coded video data reformatting block for pipelined image processor. Increased marketability of chip by enabling video data to drive 12 different output formats.* Coded column processor for 10-bit, 15fps VGA image sensor timing controller.* Structured code to target synthesis and testability. All blocks first-time functional.* Brought timing controller expertise into sensor development team.Created System-on-Chip CCD-based digital camera controllers by integrating logic with IP blocks and RAMs.* Experienced with embedded cores, re-usable IP, RAMs, DFT (scan, JTAG, BIST).* Accustomed to multiple circuit blocks interfaced using common bus and multiple clock domains existing throughout chip.* Exposed to Tcl-based synthesis timing constraints for Synopsys Design Compiler.* Understands how physical synthesis and static timing analysis drive timing closure.* Guaranteed uP/ASIC interface timing for MFP SoC using PrimeTime STA.

Strengthened HP ASIC foundry business through customer-focused back-end solutions.* Performed floorplanning, place-and-route, and physical verification for 9 chips.* Managed/characterized custom circuit layouts, providing familiarity with artwork.* Guaranteed functionality and timing specifications for circuits and pad drivers at both schematic and artwork stages through extensive SPICE simulation.* Managed verfication of design fixes using FIB to reduce risk in mask turns.* Key customer interface responsible for IC technical implementations.Developed and released to production test hardware and software for 9 digital CMOS ASICs.* Debugged wafer and final test programs on Sentry s15, s50, s9000FX, HP83000 F330 testers.* Emphasis placed on manufacturability.* Characterized final tests over process, voltage, and temperature using schmoos to determine chip margin and repeatability before release to production.* Managed layout of final test boards prior to release to ensure production quality hardware.* Created static, speed, and IDDQ production ATPG vectors using industry-standard tools. Simulated vectors at PVT corners to guarantee margin in production.

Developed and released to production test hardware and software for 10 analog bipolar ICs.* Debugged wafer and final test programs on Sentry s80 tester.* Designed custom test boards by selecting hardware components necessary to test and characterize ICs. Developed CAD drawings necessary for technician to build custom boards.* Managed layout of final test boards prior to release to ensure production quality hardware.* Held informative reviews to communicate test coverage and capabilities to other functional areas within organization.* Wrote precise, clear documentation describing test plans and implementation.