Gary Hartman Email and Phone Number

Lead electrical engineer for reentry systems electronics on the Ground Based Strategic Deterrent (GBSD) program. Also involved in IRAD, including development of extended range ultrawide bandwidth (UWB) mesh network radio for use in several products.

Director of Engineering for the Advanced Solutions Group at Geon Technologies, LLC, providing technical leadership for advanced software and firmware solutions in the defense community. Duties include IRAD development and leadership, technical management, proposal contributions, mentorship, etc.

Technical SME and IRAD leader after Electronic Systems group moved to project oriented leadership (no engineering matrix). Highlights include:Embedded software for a three-core Analog Devices DSP to interface with an FPGA, eMMC, and set up and control three Time to Digital Converters (TDC’s) memory mapped to the DSP through the FPGA.FPGA firmware (VHDL) for an FPGA interfacing to three multi-channel ADC’s (16 channels total), three TDC’s, high speed serial interface and an Analog Devices DSP. The circuit measures laser and IR returns for the purpose of mapping the ground. Systems and Project Engineer for Textron's Common Unmanned Surface Vehicle (CUSV) IRAD: Effort was to bring full autonomy to the CUSV with sensors including radar, AIS and camera video. We also partnered with Dahlgren Naval Surface Warfare Center to integrate a 0.50 cal weapon system and Hellfire missile launcher. https://www.youtube.com/watch?v=xMZmTZWb0ys.

Provided engineering leadership for Textron’s Electronic Warfare (EW) group, ~100 engineers of all disciplines (mechanical, electrical, software and systems) in a matrixed organization. Duties included management of ~$6M IRAD each year and approval of IRAD plans, project estimation, proposal writing and review, design reviews, recruiting and interviewing, processes and procedures, and mentoring. I also maintained a significant technical role in several IRAD projects.

Around 2009 I began leading technical projects, many of which I had complete technical authority over. I currently have a hybrid role – managing teams but also directly contributing to highly technical solutions and problems due to my experience. I’m also involved in many proposal efforts, estimates, IRAD plan generation, design reviews, technical presentations (PDR, CDR, etc.), recruiting and interviewing, and mentoring. Technical highlights from my past few years include:- Project engineer and system designer for a high powered (4 KW) Electronic Warfare (EW) threat simulator operating from 4 GHz to 18 GHz with a six foot RF dish and TWT amplifiers on a pedestal that optically tracks a target aircraft. The system was on a trailer with its own generator and programmable to simulate ground based EW threats for the purpose of testing flying aircraft.- Project Engineer and system designer for a low power (+80 dBm ERP), portable range threat simulator mounted on a tripod with a four foot RF dish. The system is programmable from 2 GHz to 18 GHz and capable of CW output using two MPM amplifiers.- Project Engineer for a major redesign and obsolescence refresh of a flight line radar simulator test system. The redesign included an FPGA, microprocessor and software upgrade on the main control circuit card.- Project Engineer and system designer for the Man Portable Aircraft Survivability Trainer (MAST), a system that simulates missile plumes and stimulates optical sensors on aircraft for the purpose of pilot training. The system incorporated UV LEDs for stimulus, IR camera for aircraft targeting and recording, and an embedded computer to control the system and record video on a solid state hard drive.

My primary responsibilities included circuit card design, FPGA firmware and embedded software development. I've designed with Intel Altera, Xilinx and Lattice FPGAs; have experience with Nios II and Microblaze softcore processors as well as Microchip, Atmel, and PowerPC processors. I've also designed with DDR memory, high speed LVDS interfaces and many communication interfaces such as Ethernet, USB, VME, etc. Some project highlights are:- Circuit card design and VHDL for a Xilinx Spartan FPGA with 16 ADC interfaces to microphones capturing the sonic waves of passing bullets. The design is similar to a digital oscilloscope in operation with the FPGA triggering on sonic thresholds and capturing data. The purpose of the design is to determine the direction of a fired bullet (my co-patent for an adaptable threshold was part of this project).- Xilinx Virtex VHDL firmware that included an embedded PowerPC 405, several 2.5 Gbps RocketIO interfaces, multiple RLDRAM-II memory interfaces, and an Ethernet soft core. Functions implemented in the FPGA were memory mapped to the PowerPC for software control. Purpose of the board was to manage an electronic warfare simulation timeline and channel alignment for eight combined RF synthesizers by steering RF pulses to available digital synthesizer channels.- Circuit card design and VHDL for a Xilinx Virtex FPGA and external PowerPC processor used as the motherboard for an aircraft radar test system. The FPGA reads stimulus vectors from an external memory and controls attenuators, PLLs, switch paths, and steering DACs in the RF subsystem to generate the desired RF output. The FPGA also modulates vectors to perform Doppler shift and antenna scan patterns on the RF output. In addition to the processor and FPGA, my hardware design included SDRAM, flash ROM, an Ethernet transceiver, dual port RAM, and an interface to a memory flash card. The PowerPC ran an embedded OS and our custom software.