Implemented and supported customer physical design flows using Titan, Shape Based Router (SBR), Custom Designer GCR and ICC-CD co-design environment.• Created TCL scripts, customizing and automating design flows for customer specific applications reducing scheduled time to tape-out. Applications included differential pairs, bus routing, matched length routing, symmetric routing and river routing.• Setup and supported the Titan base platform, specifically schematic driven layout, iPDK and PyCell development.

Responsibilities include top-level floor-planning, power planning, routing and power analysis, special net routing and top-level chip assembly using Magma. These tasks required the creation of TCL scripts to develop a repeatable design flow for rapid cycle time through the chip assembly process. Responsibilities also included physical verification of all custom analog blocks and the assembled top-level chip using Mentor Calibre, maintenance and enhancing the physical verification TCL scripts, coordinating final physical design reviews and tape-out to the fabrication foundry. Completed and taped-out two Media PC designs in 130nm and 65nm.

Responsibilities included implementation and maintaining the analog mixed signal custom design flow, implementation of a big-digital small-analog place and route flow, managing an international team completing chip assembly of AMCC products, managing the development and maintenance of process design kits in 180nm, 130nm and 90nm, budgeting, hiring, performance reviews, tool evaluations and purchases. Scripting languages included SH, AWK, Skill, AMPLE. EDA tools include Silicon Ensemble, First Encounter, Virtuoso Layout, Calibre DRC & LVS and Apollo.

Primary responsibilities included defining and implementing the physical chip assembly and physical verification flows, full hierarchical floor-planning, place and route using Cadence Preview and Cell3, standard cell and mega cell abstract generation and physical verification. Dracula DRC and LVS command (deck) file support.

As a lead consulting engineer for the Spectrum Services Group, responsibilities included assignments at customer sites to implement and support Cell3 place and route methodologies, library physical design development, library abstract generation and Design Framework technology file support.

Layout and verification of CMOS integrated circuits for the 2200/400 CPU chip set. Updated and maintained verification command files. Wrote mask design utility programs.In 1989 was transferred to San Diego, CA semiconductor facility. Responsibilities included verification of all CMOS standard cell and IP libraries before the release to internal customers. This included running all models through net list generation, automated place and route, final GDSII stream file generation and physical verification. Developed and maintained Dracula and ISS (now Synopsys Hercules) post-processing and mebes command files to port UNISYS designs to second source design rules.

As group leader, initiated and maintained a Design Services Group, prepared a department procedures specification, performed second checks for completed projects prior to the mebes data release to the mask shop, generated and coordinated mebes databases between design engineering, mask shop and the fabrication facility and managed an electronic database storage system.