Gary Patton
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Gary Patton Email & Phone Number

Technologist and Business Executive - Retired at Self
Location: Saratoga Springs, New York, United States 15 work roles 3 schools
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Role
Technologist and Business Executive - Retired
Location
Saratoga Springs, New York, United States

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Gary Patton is listed as Technologist and Business Executive - Retired at Self, based in Saratoga Springs, New York, United States. AeroLeads shows a matched LinkedIn profile for Gary Patton.

Gary Patton previously worked as Corporate Vice President - General Manager, Design Enablement & General Manager, Components Research at Intel Corporation and Corporate Vice President and General Manager, Design Enablement at Intel Corporation. Gary Patton holds Ph.D., Electrical Engineering from Stanford University.

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Self

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About Gary Patton

Broad executive management experience including business line management, technology and product development, design enablement, leading-edge research, and manufacturing operations. #designenablement http://intel.ly/designenablement

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Gary Patton's current company

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Self
Self
Technologist and Business Executive - Retired
Scottsdale, AZ, US
AeroLeads page
15 roles

Gary Patton work experience

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Technologist And Business Executive - Retired

Self

Scottsdale, Az, Us

Corporate Vice President - General Manager, Design Enablement & General Manager, Components Research

Current

Santa Clara, California, Us

Feb 2022 - Present

Corporate Vice President And General Manager, Design Enablement

Santa Clara, California, Us

Dec 2019 - Feb 2022

Founding Partner

Current
Dl & Bj Properties, Llc

Real Estate Development

Jan 2016 - Present

Chief Technology Officer And Senior Vice President Of Worldwide R&D And Design Enablement

Malta, Ny, Us

Responsible for developing GLOBALFOUNDRIES' differentiated process and packaging technologies and design enablement, building a world-class R&D team and culture, driving key customer engagements and promoting GLOBALFOUNDRIES in external industry forums through invited keynote and panel talks. Developed highly optimized and differentiated technologies thru Design-Technology Co-Optimization (DTCO) and strong collaboration with key customers. Drove 6X reduction in Design Enablement critical bug rates and 2X improvement in bu resolution time. 2017 recipient of the IEEE Frederick Philips Award for outstanding accomplishments in the management of research and development.

Jul 2015 - Dec 2019

Vp, Semiconductor Research & Development Center & Ieee Fellow

Ibm Microelectronics

Management of IBM’s ~1600-person semiconductor research & development organization. Responsible for development of IBM’s entire portfolio of leading edge process and packaging technologies, design enablement, and the successful ramp of IBM's Server Processors & customer OEM ASICS products at industry-leading performance over multiple technology nodes. Responsibilities also include management and growth of IBM's extensive R&D alliance partnerships and growth of key customer engagements. Member of IBM’s Corporate Growth & Transformation Team (top 300 IBM executives) since 2007.

Jun 2007 - Jun 2015

Vp, Technology Development & Design Enablement

Ibm Microelectronics
Apr 2005 - Jun 2007

Vp & Gm, Head & Media Business Unit; Gm, San Jose Site

Ibm / Hitachi Gst

Responsible for the worldwide development, manufacturing, and profitability of $1B+ advanced magnetic heads and media for Hard Disk Drives. Managed successful integration of Hitachi and IBM head and media technology organizations following merger in January 2003. Restructured operations to improve profitability (PTI) 10pts and imprve execution on new product introductions. Developed San Jose site rezoning strategy with city to reduce site operating expenses. Excellent record achieved for San Jose site on environmental, safety, security, ISO compliance, and site personnel issues.

Feb 2002 - Apr 2005

Director, Wireless Business Line

Ibm Microelectronics

Drove "start up" business in IBM MIcroelectronics that became industry leader in RF technologies (e.g., SiGe HBT & RFSOI technologies). Increase revenue year-to-year despite industry downturn, increased profitability , and improved customer satisfaction (best customer survey scores in the division). Lead cross-functional team effort between business line, manufacturing, development, and finance to double gross profit %. Managed customer relationships, partnerships, and business negotiations.

Apr 1999 - Feb 2002

Executive Assistant To Ibm Senior Vp

Ibm Corporate

Supported Senior VP responsible for IBM's Microelectronics, Storage, and Display Divisions.

Oct 1998 - Apr 1999

Manufacturing Fab Superintendent

Ibm Microelectronics

Managed 24/7 manufacturing production organization. Responsible for all new technology piloting and early production supply commitments. Increased manufacturing line productivity 20%, improved cycle time performance from 15 days over plan to 10 days under plan, and met all supply commitments on logic and DRAM products.

Jul 1997 - Oct 1998

Manufacturing Yield & Characterization Functional Manager

Ibm Microelectronics

Managed manufacturing engineering organization responsible for yield learning on all products, electrical and physical characterization, inline manufacturing defect analysis, and facility production and characterization information systems. Received IBM Division Award for yield accomplishments.

Jul 1995 - Jun 1997

Senior Technology Development Manager, 64Mb Dram Program

Ibm Microelectronics

Drove successful qualification and technology transfer into volume manufacturing of 64Mb DRAM products. Achieved record yields at a DRAM technology qualification and received IBM Division Award and General Manager's Excellence Award for Leadership.

Nov 1992 - Jun 1995

Senior Technology Development Manager, Sige Bicmos Program

Ibm Microelectronics

Managed Advanced SiGe BiCMOS technology development team. Technology became basis for IBM's leadership RF and Analog BiCMOS technology offerings.

Sep 1991 - Nov 1992

Research Staff Member & Manager

Ibm Research

Managed Advanced Bipolar/BiCMOS technology department and developed IBM's breakthrough SiGe Heterojunction Bipolar Transistor (HBT) Technology. Established world record for silicon transistor speed, tripling previous record, and resulting in articles in New York Times, Business Week, Scientific American, etc. SiGe HBT work featured at 2004 International Electron Device Meetings 50th Anniversary event as top innovation of 1987. Received IBM Outstanding Technical Achievement Award for development of SiGe HBT technology. Received IBM Research Division Award for leadership of Bipolar Technology Qualification Task Force.

Aug 1986 - Aug 1991
3 education records

Gary Patton education

Ph.D., Electrical Engineering

Stanford University

M.S., Electrical Engineering

Stanford University

B.S., Electrical Engineering

Ucla
FAQ

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What company does Gary Patton work for?

Gary Patton works for Self.

What is Gary Patton's role at Self?

Gary Patton is listed as Technologist and Business Executive - Retired at Self.

Where is Gary Patton based?

Gary Patton is based in Saratoga Springs, New York, United States while working with Self.

What companies has Gary Patton worked for?

Gary Patton has worked for Self, Intel Corporation, Dl & Bj Properties, Llc, Globalfoundries, and Ibm Microelectronics.

How can I contact Gary Patton?

You can use AeroLeads to view verified contact signals for Gary Patton at Self, including work email, phone, and LinkedIn data when available.

What schools did Gary Patton attend?

Gary Patton holds Ph.D., Electrical Engineering from Stanford University.

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