Gary Petty Email and Phone Number
Gary Petty's Location
Fort Collins, Colorado, United States, United States
Gary Petty's Contact Details
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About Gary Petty
The experience at Xpeerant and Techmate has resulted in a wide range of corporate management experience and extensive experience accross practially every technical discipline has provided a truely rewarding career.Total technical experience includes:aix, asic, assembly language, atp, budget analysis, c, c++, cad, cadence, calibration, circuit design, computer hardware, course development, cpu, customer relations, cvs, data acquisition, database administration, digital design, digital signal processing, dos, drivers, ethernet, functional verification, graphical user interface, hard drives, hardware design, ide, imaging, isa bus, management, memory design, netbios, networking, operating systems, oscilloscope, pci/pcix/pci express, perl, verilog pli, power supplies, various programming languages, project management, proposal writing, radio cicruit and systems design, ram interface design, SAS, SATA, SCSI, shell scripting, signal generators, digital simulation, writing specifications, supervisory skills, tcl/tk, tcp/ip, team management, technical analysis, telecommunications, test equipment, token ring, training, unix, USB, verilog, SystemVerilog, vhdl, video, x86 processor, ARM processor, xml, xslt.Specialties: Specman e, SystemVerilog, OVM, VMM, Mixed-Signal, VerilogAMS
Gary Petty's Current Company Details
Gary Petty Work Experience Details
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Uvm Verification EngineerMit Lincoln Laboratory Mar 2022 - PresentLexington, Ma, UsInvolved in ASIC UVM Verification development to test complex devices using Questasim simulator. Project requires special verification techniques using SystemVerilog and Matlab to generate test vectors and expected results using complex math functions and extensive knowledge of the UVM Verification Methodology (yah VM squared). Developed several UVM test benches for multiple blocks of top level chip.
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Chief Executive OfficerXpeerant Inc. Mar 1996 - PresentSpring Hill, Tennessee, UsManagement and operation of Xpeerant Inc. Xpeerant has set a goal of reaching annual revenues of $20,000,000 by committing to 100 contract placements by the close of 2015. Strategic goals in order to reach this point include achieving growing our sales and recruit staff to meet these goals. -
Design Verification EngineerTexas Instruments Oct 2009 - Jun 2013Dallas, Tx, UsSetup and maintain regression of Specman e verification suite for a Memory Cache Controller. Position involved createing maintaining Specman e BFM's, Sequences, test scenarios, testbench, coverage metrics and test plans and reporting weekly coverage analysis in department meetings.A follow-on project in the DLP group involved manageing a team of 3 engineers in developing a test suite for a combination MIPI and SPI serial bus interface to an analog varactor. Test environment included using OVM and SystemVerilog along with VHDL RTL code to verify functionaligy of the device in a mixed-signal environment. In addition to writting test cases and developing the digital test bench, the project included a substantial amount of mixed-signal verification using Verilog AMS and running mixed analog/digital simulations in Virtuoso to verify operation of both digital and analog portions of the design. Also in the DLP group, an additional assignment included developing a mixed-signal test environment to verify DLP chips using VerilogAMS to stimulate a spice netlist in order to verify the operation of both digital and analog portions of the design. This effore resulted in a change in the verification of DLP chips in the department which greatly reduced simulation, verification and development time to complete a project. -
Verification Engineer/System Verilog/VmmSun Microsystems Aug 2008 - May 2009Palo Alto, Ca, UsResponsible for setting up and maintaining a VMM test environment for a SOC high end tape drive chip. The environment used VMM/RAL Register test features, SV Assertions, Randomized Stimulus and coverage checking in order to quickly obtain a high level of coverage of the chip with relatively few test programs. The environment provided high level tasks to enable other team members quickly generate tests for specific features and provided self checking to allow those tests to be added to the regression suite. -
Verilog TrainerSutherland Hdl Consulting Jan 2008 - Apr 2008Worked with Stuart Sutherland to become a training specialist for System Verilog Design and Verification classes. Stuart Sutherland is a member of the System Verilog Standards committee and one of the first Verilog trainers from the advent of Verilog HDL. Worked with Mr. Sutherland on several different classes and team-taught several sessions. Became proficient in System Verilog. Mr. Sutherland's company was bought out recently which required dissolution of our agreement to comply with the requirements of the purchasing company.
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Design/Verification EngineerAvago Technologies May 2006 - Jan 2008San Jose, Ca, UsResponsible for design and verification of 3 memory test chips including edram and static RAM (SRAM) memory modules and SERDES/PCIE modules. Created test environment and testbench to verify BIST and BISR operation and exercise JTAG TAP Controller to setup various tests thru the TAP Test Register. Responsibilities included defining chip specifications, test plans and implementation of such. Verification was accomplished using a system verilog test bench for directed tests for randomly generated tests.Also performed physical design of custom microprocessor block using Synopsys TIGER Physical Design Flow modified by Avago Technologies Design Automation group. Tasks consited of floorplanning, place, route, physical compiler, formal verification, static timing, DRC and LVS checks in order to deliver a DRC/LVS clean GDSII and Milkyway database for handoff to top level chip physical design team. Also assisted with functional verification of microprocessor and some synthesis. -
PresidentTechmate Inc. Mar 1996 - Sep 2006Founder, President and CEO, ASIC Design ConsultantTechmate Inc. was formed to compete against the big job shops and their high markups with low service to the contractors whom their very business purpose should be to serve.
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Digital Design/Verification EngineerAlereon, Inc Nov 2005 - May 2006Performed coverage analysys using Cadence Incisive tools and ncverilog to determine test requirements for a Wireless USB Media Access Controller (MAC). Wrote test plan and implemented test plan with 2 other verification engineers to accomplish 98% coverage of digital portion of mixed-signal custom IC device. Testbench was written in System Verilog. Test cases were written predominately in the c programming language with a few modules written in ARM assembler code while MAC packets were verified using random generated test patterns in Specman e. Led the verification team to bring block coverage up from 50% to 98% within 4 months.
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Digital Design Verification EngineerConformative Systems Inc Aug 2004 - Aug 2005Setup design verification environment for an XML/XSLT Acceleration chip. Design/Verification environment included verilog, System C, C/C++, shell scripts, perl scripts, CVS revision control and co-simulation of System C and Verilog RTL code. Wrote cache modules with monitoring capability for debug and facilitated loading with memory image files to accelerate simulations.Also wrote tests to perform BIST and exercise JTAG TAP controller. Simulator used was NCVerilog with simvision used for post simulation analysis. Was responsible for detecting over 173 bugs within a 5 month period. Implemented Cadence Assertion Based Simulation assertion and coverage checking into RTL netlist code for improved failure detection and test coverage.
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Digital Design/Verification EngineerIntel Feb 2004 - Aug 2004Santa Clara, California, UsWrote VHDL RTL code for the Traffic Control and Packet Checker block of the Advanced Switching core for PCI Express interface bridge. Developed major module level Specman e testbench and BFMs for verification of AS Up stream blocks with randomly generated packets. Testbench included random packet transmission, receipt of packets, scoreboarding for packet checking and coverage modules to help improve test coverage of test scenarios. Assigned task was completed ahead of schedule. -
Digital Design/Verification EngineerSharp Microelectronic Tech Sep 2003 - Feb 2004Responsible for integrating ARM Intellectual Property into an SOC device using VHDL. Design duties included modification to UART, USB and CLCD cores. Designed memory wrappers for SDRAM, integrated standard memory devices into design and wrote BIST tests and tests using JTAG TAP controller. Verification duties included writing 16c550 Uart, CLCD and USB tests in the c programming language as well as Specman e and simulating at the system level using ModelSim. Tests included interrupt services routines to simulate operation of the device in a system.
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Digital Design Verification EngineerLsi Logic Corp Aug 2002 - Sep 2003Setup system verification environment in SiCADA for a Serial-ATA (SATA) ASIC. Environment included QuickBench, Cynlib C++ Library, C code firmware, Verilog, TCL/TK and shell scripts. Testbenches included both host and device models. Follow-on project was a Serial-Attached-SCSI (SAS) ASIC and a Fibre-Channel ASIC in a similar environment making wide use of reuseability. Tests were predominately written in C++. Firmware emulation was utilizing Virtual CPU to emulate an 80196 processor with the firmware code written in C.
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Vhdl Training InstructorCadence And Esperan Corps Apr 2000 - Aug 2002Contracted with Cadence and Esperan on an as-needed basis as a contract trainer. Presented training classes for Cadence and Esperan. Classes included Verilog Basic Class, Verilog Advanced Class, VHDL Basic Class, TCL/TK Programming Class, Perl Language Class, and ASIC Design Verification Class. Assisted with course development and instructor certification programs.
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Network Processor Verification EngineerTrebia Networks Nov 2001 - Apr 2002Wrote VERA verification test cases for a Storage Network Processor SOC. The chip consisted of a TCP engine and Gigabit Ethernet interface controlled by an embedded RISC processor. Test cases verified operation of FIFOs and general TCP/IP operation between host processor, fibre channel, iSCSI and Ethernet connection. Used VERA for verification Language, VCS simulator, CVS revision control and LSF for CPU resource sharing.
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Design/Verification EngineerLsi Logic May 2000 - Nov 2001San Jose, Ca, UsVerification of microprocessor interface to SCSI target chip. Created verification environment using SiCADA to integrate the design tools with revision control and bug tracking. Wrote over 25 Specman e test scenarios and BFM to verify functional operation of microprocessor interface block.Design and verification of IDE controller with advanced Cache circuitry using VHDL. Synthesis using Synopsys Design Compiler and LSI proprioritory tool set. Also worked on a mass storage Read Channel Device with design and verification responsibilities using Verilog HDL, Quickbench verification tool, and SiCADA Design Environment. -
Design/Verification EngineerNational Semiconductor Corp Mar 1999 - May 2000Project leader on the CPU block of a System-On-A-Chip project using Verilog HDL, Vera and the SiCADA designManager environment. The chip included a x486 class microprocessor, north PCI bridge, south PCI bridge, andSuper IO blocks. Preformed EBEAM probing, fault grading, scheduling, team management, test bench development and test vector conversion. Responsibilities included RTL design, functional verification, synthesis and static timing analysis using AMBIT BuildGates, and managing the development environment.
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Design/Verification EngineerSymbios Logic Nov 1997 - Mar 1999Responsible for design and verification of SCSI Enclosure Systems portion of a differential SCSI target chip. Design included an ARM core along with ASB and APB peripherals such as GPIO, UART, I2C, RAM Block, ROM Block and Test Interface Controller. Also worked on converting a P1394 design to a new pinout to conform to a standard part of the same design. Ran existing verification tests and developed new verification tests to improve test coverage. Used Cover Scan to determine level of verification test coverage of Verilog RTL code and Zycad to determine fault grade level of gate netlist. Responsibilities included RTL design, synthesis and timing analysis using Synopsys and BuildGates. Also configured and synthesized a SAND USB core per customer's requirements. Managed the design environment using Silicon Arena and Vera. -
Embedded Processor Design/Verification EngineerNational Semiconductor Corp Apr 1996 - Nov 1997Responsible for developing test vectors for an embedded 80486 class microprocessor and peripherals chip. Wrote Verilog PLI code in C to provide special interfaceing functions to the simulator. Wrote several C language utilities to aid in test vector production. Developed a verilog tester model to verify timing and accuracy of test patterns generated from test vectors. This system enabled test patterns to be verified in simulation much cheaper than using expensive tester time to resolve test pattern problems.
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Embedded Processor Verification EngineerAdvanced Micro Devices Corp Sep 1995 - Apr 1996Developed module and system level verilog tests to verify the operation of the LCD Controller portion of an 80486 class embedded microprocessor system. Wrote utilities in TCL/TK to emulate the LCD with data stored by the verilog simulation. Also wrote C language utilities to create simulator input files from bit mapped images to be used in testing the LCD module. Also wrote tests to verify JTAG operation. Managed the design environment using SiCADA.
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Design/Verification EngineerNcr Microelectronics (Now Lsi Formerly Symbios) Apr 1990 - Sep 1995Developed design and test code in Verilog, VHDL and Mentor 8.x for various ASICs. ASICs included target SCSI, asynchronous controllers, serial communications controller, target PCI-IDE and PCI macro. Developed test patterns in Verilog HDL, VHDL and WISIL. Worked in CAD Support for 1 year developing and supporting NCR's CAD tools that verified tester compatibility of ASIC test vectors. Also performed fault grading using Zycad and IKOS hardware accelerators. A technical report was written and presented for internal use describing the "Event Driven vs. Time Dependent Test Method" which was developed and used to improve functional verification and fault grading. This method also greatly reduced the time required to develop test patterns. Also automated device timing characterization with Verilog HDL. Due to software experience assisted with writing DOS device drivers for completed ASICs.
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Design/Test EngineerIbm Corp Aug 1988 - Mar 1990Developed test plans and test software for testing various components of the AIX operating system. Software included device drivers that performed functions similar to NET BIOS and LAN Manager for ethernet and token ring adapters, display adapters, and hard drive adapters on both ISA and Micro-Channel busses.
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Firmware Design EngineerHoneywell Corp Feb 1988 - Aug 1988Part of a design team developing a hand held PC compatible computer. Had both hardware and software responsibilities. Hardware design responsibilities included design of timer, interrupt controller, and various I/O portions of circuitry. Firmware (80286) included ROM BIOS modules: time of day, system timer tick, printer, serial communications, video services and hard drive interface.
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Test EngineerE-Systems Corp Nov 1987 - Feb 1988Wrote Acceptance Test Proceedures for electronic enclosures for aircraft servo systems. Exceeded client's expectations by completing ATP's in half the scheduled time.
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Sw/Firmware Design EngineerUnisys Corp. (Formerly Sperry Corp Jan 1986 - Nov 1987Part of design team developing a 6-processor digital signal processor for a high speed data link communication system. Designed the I/O and mux/demux gate array portion of the digital signal processor using Mentor Graphics Workstation. (This mux/demux was very similar to the digital switches used in the telecommunications industry.) The mux/demux was capable of processing many channels of data at various data rates to accommodate a wide range of user data. Also wrote System BIT firmware in the C programming language and 68020 assembler. The System BIT was capable of 85% fault detection for the data link system.
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Systems EngineerGeneral Electric Corp Jan 1985 - Jan 1986Principle engineer responsible for establishing design requirements for an Automated Test System consisting of 5 HP3497A Data Acquisition Systems, 3 test multi-meters, 32 IBM-XT Computers, 8 Temperature Chambers and Controllers, Special Built Equipment and 1 IBM AT Computer. Wrote design requirements specification, developed software standards and conventions and supervised 2 programmers and 3 technicians during development of ATE system.
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Design EngineerSperry Corp Dec 1979 - Jan 1985Responsibilities included many aspects of developing digital data link communications systems. As a systems engineer, wrote requirements specifications, statement of work, design proposals, Prime Item specifications, and detailed studies on may portions data link system. This included RF subsystem, digital signal processor, power system, software requirements, test requirements and interfacing requirements. Performed several technical analysis for various portions of the data link system to include: RF Power Budget analysis, digital signal processor worst-case timing analysis, circuit analysis of receiver-transmitter networks, frequency synthesizer, phase lock loop and performed reliability analysis of several portions of the data link system. As a design engineer responsibilities have included the design of a high power density power supply, transmitter subsystem, the mux/demux portion of the data link signal processor, automated test system for testing data link system and micro processor control assemblies.
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Circuit Design EngineerAustron Inc Apr 1979 - Dec 1979Designed and prototyped Austron Model 1295C Distribution Amplifier capable of accepting 0.1 to 10.0 MHz and distributing to 36 outputs. Responsibilities included circuit design, cost estimate, test and evaluation, conducting design review meetings and supervising production of first line units.
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Age Design EngineerMcdonnell Douglas Corp Sep 1978 - Apr 1979Wrote AGE/GSE recommendations on test equipment for F4, F18 and AV8 Aircraft Avionics Systems.
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Circuit Design EngineerScientific Communication Inc Oct 1977 - Sep 1978Designed and prototyped various components of receiver systems. Components consisted of RF and IF amplifiers, Phase Locked Loop and Local Oscillator. Performed insertion loss and sensitivity calculations and measurements.
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Electronic Warfare SpecialistU.S. Air Force Jun 1972 - Oct 1977Randolph Afb, Tx, UsCLASSIFIED. -
Electronic TechnicianTektronics Inc Nov 1970 - Jun 1972Performed repair, calibration and periodic maintenance of various models of Tektronics' oscilloscopes, transistor curve tracers, signal generators, etc.
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Asst. ManagerRadio Shack Sep 1969 - Nov 1970Due to excellent knowledge of electronics and personal skills was given responsibility of assisting with the management of a Radio Shack store at an early age.
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Radio RepairmanDallas Power & Light Jun 1969 - Sep 1969Responsibilities included maintenance and repair of radio communications equipment and cleaning the shop every darned day
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Sales ClerkRadio Shack Nov 1967 - Jun 1969Assisted with the sale of electronic equipment, devices, supplies and systems. Excellent knowledge of electronics helped to make our store one the leading stores in the DFW area.
Gary Petty Skills
Systemverilog
Open Verification Methodology
Specman
Verilog
Asic
Perl
Shell Scripting
Unix
Soc
Rtl Design
Vhdl
Hardware Architecture
Integrated Circuit Design
Ic
Mixed Signal
Debugging
Eda
Gary Petty Education Details
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Weber State UniversityElectronics
Frequently Asked Questions about Gary Petty
What company does Gary Petty work for?
Gary Petty works for Mit Lincoln Laboratory
What is Gary Petty's role at the current company?
Gary Petty's current role is Design Verification Engineer at Xpeerant Inc..
What is Gary Petty's email address?
Gary Petty's email address is ga****@****ant.com
What is Gary Petty's direct phone number?
Gary Petty's direct phone number is +197022*****
What schools did Gary Petty attend?
Gary Petty attended Weber State University.
What skills is Gary Petty known for?
Gary Petty has skills like Systemverilog, Open Verification Methodology, Specman, Verilog, Asic, Perl, Shell Scripting, Unix, Soc, Rtl Design, Vhdl, Hardware Architecture.
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