Gary Petty Email & Phone Number

Lexington, MA, US

Involved in ASIC UVM Verification development to test complex devices using Questasim simulator. Project requires special verification techniques using SystemVerilog and Matlab to generate test vectors and expected results using complex math functions and extensive knowledge of the UVM Verification Methodology (yah VM squared). Developed several UVM test.

Spring Hill, Tennessee, US

Management and operation of Xpeerant Inc. Xpeerant has set a goal of reaching annual revenues of $20,000,000 by committing to 100 contract placements by the close of 2015. Strategic goals in order to reach this point include achieving growing our sales and recruit staff to meet these goals.

Dallas, TX, US

Setup and maintain regression of Specman e verification suite for a Memory Cache Controller. Position involved createing maintaining Specman e BFM's, Sequences, test scenarios, testbench, coverage metrics and test plans and reporting weekly coverage analysis in department meetings.A follow-on project in the DLP group involved manageing a team of 3.

Palo Alto, CA, US

Responsible for setting up and maintaining a VMM test environment for a SOC high end tape drive chip. The environment used VMM/RAL Register test features, SV Assertions, Randomized Stimulus and coverage checking in order to quickly obtain a high level of coverage of the chip with relatively few test programs. The environment provided high level tasks to.

Worked with Stuart Sutherland to become a training specialist for System Verilog Design and Verification classes. Stuart Sutherland is a member of the System Verilog Standards committee and one of the first Verilog trainers from the advent of Verilog HDL. Worked with Mr. Sutherland on several different classes and team-taught several sessions. Became.

San Jose, CA, US

Responsible for design and verification of 3 memory test chips including edram and static RAM (SRAM) memory modules and SERDES/PCIE modules. Created test environment and testbench to verify BIST and BISR operation and exercise JTAG TAP Controller to setup various tests thru the TAP Test Register. Responsibilities included defining chip specifications, test.

Founder, President and CEO, ASIC Design ConsultantTechmate Inc. was formed to compete against the big job shops and their high markups with low service to the contractors whom their very business purpose should be to serve.

Performed coverage analysys using Cadence Incisive tools and ncverilog to determine test requirements for a Wireless USB Media Access Controller (MAC). Wrote test plan and implemented test plan with 2 other verification engineers to accomplish 98% coverage of digital portion of mixed-signal custom IC device. Testbench was written in System Verilog. Test.

Setup design verification environment for an XML/XSLT Acceleration chip. Design/Verification environment included verilog, System C, C/C++, shell scripts, perl scripts, CVS revision control and co-simulation of System C and Verilog RTL code. Wrote cache modules with monitoring capability for debug and facilitated loading with memory image files to.

Santa Clara, California, US

Wrote VHDL RTL code for the Traffic Control and Packet Checker block of the Advanced Switching core for PCI Express interface bridge. Developed major module level Specman e testbench and BFMs for verification of AS Up stream blocks with randomly generated packets. Testbench included random packet transmission, receipt of packets, scoreboarding for packet.

Responsible for integrating ARM Intellectual Property into an SOC device using VHDL. Design duties included modification to UART, USB and CLCD cores. Designed memory wrappers for SDRAM, integrated standard memory devices into design and wrote BIST tests and tests using JTAG TAP controller. Verification duties included writing 16c550 Uart, CLCD and USB.

Setup system verification environment in SiCADA for a Serial-ATA (SATA) ASIC. Environment included QuickBench, Cynlib C++ Library, C code firmware, Verilog, TCL/TK and shell scripts. Testbenches included both host and device models. Follow-on project was a Serial-Attached-SCSI (SAS) ASIC and a Fibre-Channel ASIC in a similar environment making wide use of.

Contracted with Cadence and Esperan on an as-needed basis as a contract trainer. Presented training classes for Cadence and Esperan. Classes included Verilog Basic Class, Verilog Advanced Class, VHDL Basic Class, TCL/TK Programming Class, Perl Language Class, and ASIC Design Verification Class. Assisted with course development and instructor certification.

Wrote VERA verification test cases for a Storage Network Processor SOC. The chip consisted of a TCP engine and Gigabit Ethernet interface controlled by an embedded RISC processor. Test cases verified operation of FIFOs and general TCP/IP operation between host processor, fibre channel, iSCSI and Ethernet connection. Used VERA for verification Language, VCS.

San Jose, CA, US

Verification of microprocessor interface to SCSI target chip. Created verification environment using SiCADA to integrate the design tools with revision control and bug tracking. Wrote over 25 Specman e test scenarios and BFM to verify functional operation of microprocessor interface block.Design and verification of IDE controller with advanced Cache.

Project leader on the CPU block of a System-On-A-Chip project using Verilog HDL, Vera and the SiCADA designManager environment. The chip included a x486 class microprocessor, north PCI bridge, south PCI bridge, andSuper IO blocks. Preformed EBEAM probing, fault grading, scheduling, team management, test bench development and test vector conversion..

Responsible for design and verification of SCSI Enclosure Systems portion of a differential SCSI target chip. Design included an ARM core along with ASB and APB peripherals such as GPIO, UART, I2C, RAM Block, ROM Block and Test Interface Controller. Also worked on converting a P1394 design to a new pinout to conform to a standard part of the same design..

Responsible for developing test vectors for an embedded 80486 class microprocessor and peripherals chip. Wrote Verilog PLI code in C to provide special interfaceing functions to the simulator. Wrote several C language utilities to aid in test vector production. Developed a verilog tester model to verify timing and accuracy of test patterns generated from.

Developed module and system level verilog tests to verify the operation of the LCD Controller portion of an 80486 class embedded microprocessor system. Wrote utilities in TCL/TK to emulate the LCD with data stored by the verilog simulation. Also wrote C language utilities to create simulator input files from bit mapped images to be used in testing the LCD.

Developed design and test code in Verilog, VHDL and Mentor 8.x for various ASICs. ASICs included target SCSI, asynchronous controllers, serial communications controller, target PCI-IDE and PCI macro. Developed test patterns in Verilog HDL, VHDL and WISIL. Worked in CAD Support for 1 year developing and supporting NCR's CAD tools that verified tester.

Developed test plans and test software for testing various components of the AIX operating system. Software included device drivers that performed functions similar to NET BIOS and LAN Manager for ethernet and token ring adapters, display adapters, and hard drive adapters on both ISA and Micro-Channel busses.

Part of a design team developing a hand held PC compatible computer. Had both hardware and software responsibilities. Hardware design responsibilities included design of timer, interrupt controller, and various I/O portions of circuitry. Firmware (80286) included ROM BIOS modules: time of day, system timer tick, printer, serial communications, video.

Wrote Acceptance Test Proceedures for electronic enclosures for aircraft servo systems. Exceeded client's expectations by completing ATP's in half the scheduled time.

Part of design team developing a 6-processor digital signal processor for a high speed data link communication system. Designed the I/O and mux/demux gate array portion of the digital signal processor using Mentor Graphics Workstation. (This mux/demux was very similar to the digital switches used in the telecommunications industry.) The mux/demux was.

Principle engineer responsible for establishing design requirements for an Automated Test System consisting of 5 HP3497A Data Acquisition Systems, 3 test multi-meters, 32 IBM-XT Computers, 8 Temperature Chambers and Controllers, Special Built Equipment and 1 IBM AT Computer. Wrote design requirements specification, developed software standards and.

Responsibilities included many aspects of developing digital data link communications systems. As a systems engineer, wrote requirements specifications, statement of work, design proposals, Prime Item specifications, and detailed studies on may portions data link system. This included RF subsystem, digital signal processor, power system, software.

Designed and prototyped Austron Model 1295C Distribution Amplifier capable of accepting 0.1 to 10.0 MHz and distributing to 36 outputs. Responsibilities included circuit design, cost estimate, test and evaluation, conducting design review meetings and supervising production of first line units.

Wrote AGE/GSE recommendations on test equipment for F4, F18 and AV8 Aircraft Avionics Systems.

Designed and prototyped various components of receiver systems. Components consisted of RF and IF amplifiers, Phase Locked Loop and Local Oscillator. Performed insertion loss and sensitivity calculations and measurements.

Randolph AFB, TX, US

CLASSIFIED.

Performed repair, calibration and periodic maintenance of various models of Tektronics' oscilloscopes, transistor curve tracers, signal generators, etc.

Due to excellent knowledge of electronics and personal skills was given responsibility of assisting with the management of a Radio Shack store at an early age.

Responsibilities included maintenance and repair of radio communications equipment and cleaning the shop every darned day

Assisted with the sale of electronic equipment, devices, supplies and systems. Excellent knowledge of electronics helped to make our store one the leading stores in the DFW area.