Director, System Architecture
CurrentAdvancing timing solutions at the architectural level within the Communications-Enterprise-Datacenter BU.
Jan 2024 - Present
AeroLeads people directory · profile
Gary Giust, Phd Email & Phone Number
Director, System Architecture
at
SiTime
1 work email found
@sitime.com
3 phones found area 408
LinkedIn matched
✓ Verified May 2026
4 data sources
Profile completeness 100%
Current company
Role
Director, System Architecture
Location
Santa Clara, California, United States
Who is Gary Giust, Phd? Overview
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Quick answer
Gary Giust, Phd is listed as Director, System Architecture at SiTime, based in Santa Clara, California, United States. AeroLeads shows a work email signal at sitime.com, phone signal with area code 408, and a matched LinkedIn profile for Gary Giust, Phd.
Gary Giust, Phd previously worked as Sr. Mgr, Technical Marketing at Sitime and Sr. Mgr, Product Marketing at Sitime. Gary Giust, Phd holds Phd, Electrical Engineering from Arizona State University.
Company email context
Email format at SiTime
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*@sitime.com
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AeroLeads found 1 current-domain work email signal for Gary Giust, Phd. Compare company email patterns before reaching out.
Profile bio
About Gary Giust, Phd
● Passionate about driving business where it intersects technology.● Enthusiast of clock and timing, high-speed communications, RF markets, technologies and applications.● Creative, driven, thinker and doer.● Thought leader, author, speaker, teacher.
Listed skills include Semiconductors, Ic, Analog, Mixed Signal, and 14 others.
Current workplace
Gary Giust, Phd's current company
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12 roles · 29 years
Gary Giust, Phd work experience
A career timeline built from the work history available for this profile.
Sr. Mgr, Technical Marketing
Timing architecture, standards bodies, conferences, customer learning hub/collateral/webinars.
Jan 2021 - Dec 2023
Sr. Mgr, Product Marketing
Product definition and management of XOs and TCXOs targeting communications, 5G and enterprise applications.
May 2018 - Dec 2020
Ocp-Tap, Oscillator Workstream - Point Of Contact
CurrentOpen Compute Project (OCP) Timing Appliance Project (TAP) brings the community together to enable time-sensitive applications via time synchronization of data center networks. The Oscillator Workstream enables system designers to optimize data center synchronization by proper oscillator selection.https://www.opencompute.org/wiki/Time_Appliances_Project
Jul 2020 - Present
Technical Instructor
13 years teaching "Jitter Essentials" class twice annually to industry professionals. This class fulfilled 1.5 credits towards a certificate in either VLSI Engineering or Embedded Systems.
Jan 2006 - Mar 2019
Ceo/Cto
Independent test, analysis, and software services to help businesses promote, select, and qualify timing devices for new designs. Licensing of patent IP.
Apr 2010 - May 2018
Principal Application Engineer
Application support for 10+ Gbps SERDES and telecom high-speed PHYs, helping customers design-in, bring-up, and debug our silicon in their applications and labs. Technical Chair for Ethernet Alliance Backplane (IEEE 802.3ap) Subcommittee.
Oct 2007 - Apr 2010
Product Marketing Manager
Defined silicon ICs used in oscillators (XOs, VCXOs, etc.), brought them to market, and managed their business.
Jan 2007 - Oct 2007
Jan 2006 - Dec 2006
Principal Applications Engineer
Applications engineer in Timing Technology Division, defining and supporting products from concept through production. Emphasis on high-speed standards. Co-author of Perfect Timing II.
2003 - 2006
~3 yrs
Senior Staff Analog Design Engineer
Analog design engineer in the PHY Business Unit designing silicon blocks for PLL and SERDES ICs.
2001 - 2003
~2 yrs
Senior Staff Process Integration Engineer
Process integration engineer for the Foundry R&D Division, designing 0.25 and 0.13 um CMOS process technologies for optimum performance, yield, density, reliability.
1997 - 2000
~3 yrs
4 education records
Gary Giust, Phd education
Phd, Electrical Engineering
Arizona State University
Certificate, Data Science Specialization By Coursera
The Johns Hopkins University
Ms, Electrical Engineering
University Of Colorado Boulder
Bs, Electrical Engineering
University Of New Hampshire
FAQ
Frequently asked questions about Gary Giust, Phd
Quick answers generated from the profile data available on this page.
What company does Gary Giust, Phd work for?
Gary Giust, Phd works for SiTime.
What is Gary Giust, Phd's role at SiTime?
Gary Giust, Phd is listed as Director, System Architecture at SiTime.
What is Gary Giust, Phd's email address?
AeroLeads has found 1 work email signal at @sitime.com for Gary Giust, Phd at SiTime.
What is Gary Giust, Phd's phone number?
AeroLeads has found 3 phone signal(s) with area code 408 for Gary Giust, Phd at SiTime.
Where is Gary Giust, Phd based?
Gary Giust, Phd is based in Santa Clara, California, United States while working with SiTime.
What companies has Gary Giust, Phd worked for?
Gary Giust, Phd has worked for Sitime, Ocp-Tap, University Of California, Santa Cruz, Jitterlabs, and Appliedmicro.
How can I contact Gary Giust, Phd?
You can use AeroLeads to view verified contact signals for Gary Giust, Phd at SiTime, including work email, phone, and LinkedIn data when available.
What schools did Gary Giust, Phd attend?
Gary Giust, Phd holds Phd, Electrical Engineering from Arizona State University.
What skills is Gary Giust, Phd known for?
Gary Giust, Phd is listed with skills including Semiconductors, Ic, Analog, Mixed Signal, Asic, Electronics, Soc, and Jitter.
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