Advancing timing solutions at the architectural level within the Communications-Enterprise-Datacenter BU.

Timing architecture, standards bodies, conferences, customer learning hub/collateral/webinars.

Product definition and management of XOs and TCXOs targeting communications, 5G and enterprise applications.

Open Compute Project (OCP) Timing Appliance Project (TAP) brings the community together to enable time-sensitive applications via time synchronization of data center networks. The Oscillator Workstream enables system designers to optimize data center synchronization by proper oscillator selection.https://www.opencompute.org/wiki/Time_Appliances_Project

13 years teaching "Jitter Essentials" class twice annually to industry professionals. This class fulfilled 1.5 credits towards a certificate in either VLSI Engineering or Embedded Systems.

Independent test, analysis, and software services to help businesses promote, select, and qualify timing devices for new designs. Licensing of patent IP.

Application support for 10+ Gbps SERDES and telecom high-speed PHYs, helping customers design-in, bring-up, and debug our silicon in their applications and labs. Technical Chair for Ethernet Alliance Backplane (IEEE 802.3ap) Subcommittee.

Defined silicon ICs used in oscillators (XOs, VCXOs, etc.), brought them to market, and managed their business.

Support power-management IC products.

Applications engineer in Timing Technology Division, defining and supporting products from concept through production. Emphasis on high-speed standards. Co-author of Perfect Timing II.

Analog design engineer in the PHY Business Unit designing silicon blocks for PLL and SERDES ICs.

Process integration engineer for the Foundry R&D Division, designing 0.25 and 0.13 um CMOS process technologies for optimum performance, yield, density, reliability.