• Gained hands-on experience in scan insertion, scan compression, DRC analysis and coverage improvement, ATPG pattern generation and validation, analysis of SA, TDF and IDDQ faults, Simulation without timing, and MBIST insertion using Tessent tool chain.• Experience in TCL scripting.• MBIST and scan insertion on 2 small designs : - Worked on small Hierarchical designs consisting of a Parent and multiple Child cores. - Performed MBIST Insertion, Scan Stitching and DRC Cleanup, EDT and OCC Insertion. - Worked on ATPG Coverage analysis, Pattern generation and Serial & Parallel Scan pattern Simulation.

• Gained hands-on experience in HDL and various tools for Simulation (Synopsys VCS), Synthesis(Synplify pro) and FPGA Prototyping(HAPS ProtoCompiler).• Designed and developed a RISC-V disassembler tool (RV64IMAFDC) and scripts for its verification using python.• Participated in design verification and analysis of CPU prototyping project.