Gavin Grant Email & Phone Number

Irvine, California, US

Wilmington, MA, US

Digital layout of processor based platforms interfacing to analog front end devices using low power synthesis techniques including power gating. RTL to GDS2 flow using Synopsys and Cadence toolset.

- Helping with layout of small digital blocks on larger analog chips- Driving SOC Encounter to achieve necessary goals and targets for timing and congestion- Library and tool setup

GB

STA Engineer on 65nm voltage scaled multimedia ASICResponsibilities include:-- Running and analysing multiple functional STA jobs over various voltage ranges using Primetime- Maintaining Perl/TCL scripting environment- Generating ECO scripts for layout team- Generating and maintaining SDC constraints for synthesis, layout and timing sign-off for multiple.

Eindhoven, Noord-Brabant, NL

RISC processor hardening group, performing layout of advanced RISC processors targetting >500MHz clock speeds in 45nm process.Responsibilities are in floorplanning, layout and physical/timing sign-off as well as flow development.

IC Physical Design company specialising in the layout of large hierarchical SoC ASICs from RTL/Netlist to GDS2 tapeout targetting sub-90nm processes. Flow tasks include constraint definition, synthesis, floorplanning, partitioning, clock tree insertion, STA and physical verification.

Eindhoven, Noord-Brabant, NL

- Dual I/O ring specification and implementation incorporating Analogue, LVDS, DDR2, PCI, USB pad ring sections using SOC Encounter- Timing constraint generation including >200 clocks, max IP frequency 400MHz- STA with Primetime, ECO generation for layout team for timing closure- Perl script generation to support all activities

San Jose, California, US

At Cadence I assumed technical responsibility for the design of digital/mixed-signal SoC ASIC projects (RTL to GDS2), with responsibility for a small design team. This involved all steps from floorplanning to timing/physical sign-off, primarily with the Cadence tool suite.I generated and maintained technical project plans, reporting to the project manager.

Chicago, Illinois, US