Geng Chen Email & Phone Number

中国 浙江省 义乌市

Failure analysis on in-house reliability testing and customer complaint/feedback chips, drive for root-cause identifications and containment measures and corrective actions to prevent recurrence; worked as a key member in RED micro LED joint-development team with a key Korean customer, completed successfully Phase I JD activity, signed Phase II development agreement; as a backlight PDT team manager, worked with two major domestic customers to deliver products with desired performance target and reliability requirements on extremely tight project timelines

Chengdu, Sichuan, China

Photovoltaic power plant overall efficiency improvement management: defect detection/prevention; alternative supporting structure evaluation and promotion; PV panel cleaning and maintenance

Shanghai City, China

Manage the team and provide technical sales support for Key Accounts, Middle East and Africa (MEA) and Americas (NA and SA) regions – set up Company-wide technical training platform and evaluation system; developed Quality management system for JASO overseas JV Fab; lead and represented JASO in cross-company task force including EPC, Lender and Technical Advisers for Potential-Induced-Degradation (PID) failure mechanism issue resolution within 9 months, and proliferated throughout customer base; streamlined small claim business process flow

Fremont, Ca

Responsible for leading and driving R&D efforts to improve CdTe/CdS solar cell and module performance from 13% to 16.5% through process window exploration and equipment modification with in-situ thickness monitoring

Milpitas, Ca

Responsible for ensuring the reliability of VCSELs, PIN/avalanche photodiodes, DFB edge emitting laser diodes, and Integrated Mach-Zender tunable laser chips – defined reliability testing strategy for chip development, designed and set-up accelerated life test (ALT) process/procedure; analyzed data, predicted and calculated device life-time and failure-in-time (FIT) rates; performed systematic in-depth failure analysis; established and released initial FMEAs/Control Plans/Rel testing Matrix for a number of devices

Santa Clara, Ca

Responsible for maintaining, developing, and qualifying RIE processes for digital X-ray image sensor (50x50 cm2) on glass substrates (Mo/Cr Mo-only gate etch, a-Si TFT etch, diode etch, passivation etch) – achieved multi-million-dollar cost-saving new product by qualifying a Mo-only Gate (bottom-gate) etch process within 9 months; timely resolved ESD issue from line-down to normal yield; new tool/process qual

Fremont, Ca

Responsible for developing doped-LiFePO4, high-k Dielectric and on-chip integration of wavelength converting Phosphor material/processes utilizing proprietary “Combinatorial” material engineering process

Singapore

Responsible for die- and wafer-level failure analysis on advanced CMOS devices: 300-mm Cu 90- nm SOI μ-processor to 200-mm/300-mm 0.13~0.18 μm RF/high-voltage/low-power chips – performed electrical fault isolation using probe-station/curve tracing, liquid crystal analysis, emission microscopy and thermally induced voltage alteration(TIVA); conducted physical analysis through de-processing, optical microscopy, SEM/EDX/PVC, and FIB cross-sectioning; wrote technical FA reports, provided technical opinion in customer communications

Meng, Electrical Engineering

Bsc, Physics

Master Of Business Administration - Mba, Accounting And Finance