Geoffrey H. Email & Phone Number

Portland, Or, Us

Santa Clara, California, Us

Conduct full-chip design validation activities involving model bringup and end-to-end flow validation within the SoC and package-level models.Updated initial bootstrap code and configuration management software to support new SoC and package features, as well as scale from individual dielet to multi-dielet model configurations. Added new Python code to model stubbed out system component behavior. Mentored junior team members on team workflow, code quality, and debug methods. Owned execution plans for weekly bulk regressions and initial triage of failure buckets.Facilitated training and dojos for department code quality initiatives. Helped coordinate and support other facilitators and track owners.

Santa Clara, California, Us

Conduct multiple-die integration activities for next-generation Client and Device products. Advocate for standardization, optimization, and deterministic quality in platforms provided to Pre-Silicon Software enabling teams, both internal and external to the company.

Santa Clara, California, Us

Produce code that interfaces system flows run on Virtual Platform with RTL synthesized inside FPGA-based prototyping platforms used for Pre-silicon Software Validation and Integration. Debug failures involving interactions between devices and firmware running on FPGA with OS and firmware running inside Virtual Platform. Debug failures using in-system debug tools, RTL instrumentation, and log analysis. Reproduce failures from the bench in simulation and big box emulation environments for improved debug fidelity and collaboration with Design Engineers. Work with IT staff to coordinate the deployment of networking and storage infrastructure required to support the target platforms and lab spaces assigned to the team.

Santa Clara, California, Us

Perform Firmware Integration activities for IP RTL models implemented in FPGAs which interface with reference storage and sensor devices using industry standard protocols. Provide qualification content that runs in simulation, emulation, FPGA, and Silicon targets. Debug failures to root cause and provide feedback to use case requirements and test plans that help to close coverage holes.

Santa Clara, California, Us

Pre-Silicon validation of Intel® IA-32 ISA-based soft IPs in Intel’s next-generation Atom SOC product. Through use of Simulation and Emulation platforms, successfully verified integration of IP into fabrics and interrupt connectivity using Linux and small, self-checking targeted tests. Developed processes to convert binary firmware images into text files suitable for loading into Emulator memories using the Veloce API. Wrote requirements documentation for improved Emulation instrumentation and logging facilities to assist analysis of failures during triage and debug.

Santa Clara, California, Us

Performed Pre- and Post-Silicon validation of an embedded validation network that provides real-time debug and coverage visibility into key internal system state of the Intel® Core™ 4000-series desktop and mobile SOCs. Extended a C# programming API with a derivative class that added custom programming and user interaction controls used by validation customers to configure 4000-series specific features. Built an Iron-Python test bench configuration generator around this C# class and enabled to run on Linux using the Mono 2.6 CLR. Worked with validation peers from the Internal Graphics validation team to further extend data structures and methods of the custom C# class to add the ability to configure their own custom Design For Debug (DFD) features. Supported the software teams that used the API on debugging output and further enhancing the C# class for their requirements. Supported the system validation and debug tools teams across Intel® sites to root cause and document deviations from product specifications, develop required workarounds, and analyze their impact to customers.

Santa Clara, California, Us

Delivered debug configuration software tools for Post-Silicon validation of the Intel® Core™ i7 Desktop and single-socket Server products. Debugged failures on the Core™ i7 SOC’s PCIe 2.0 and DMI interconnects using serial analyzers, JTAG run control, and proprietary internal observation and debug tools.

Santa Clara, California, Us

Enabled embedded test environments to interface via chipset I2C and SMBus host controllers with custom validation hardware designed around microcontrollers, ASICs, and FPGAs. Debugged failures using protocol analyzers, processor and chipset JTAG, and simple test executables designed to reproduce failures quickly for easier analysis.

Us

Worked on PHP and MySQL backend features for SourceForge.Net. Worked with fellow Professional Services Engineers to customize individual SourceForge system installations at customer sites to add additional features or user interface changes.

Santa Clara, California, Us

Helped maintain a PERL-based automation system that first built a suite of executables written in Visual C then ran a nightly regression to check for newly introduced failures. The automation system produced HTML-based reports for developers to check for newly introduced failures.