Geoffrey H. Email & Phone Number

Portland, OR, US

Santa Clara, California, US

Conduct full-chip design validation activities involving model bringup and end-to-end flow validation within the SoC and package-level models.Updated initial bootstrap code and configuration management software to support new SoC and package features, as well as scale from individual dielet to multi-dielet model configurations. Added new Python code to.

Santa Clara, California, US

Conduct multiple-die integration activities for next-generation Client and Device products. Advocate for standardization, optimization, and deterministic quality in platforms provided to Pre-Silicon Software enabling teams, both internal and external to the company.

Santa Clara, California, US

Produce code that interfaces system flows run on Virtual Platform with RTL synthesized inside FPGA-based prototyping platforms used for Pre-silicon Software Validation and Integration. Debug failures involving interactions between devices and firmware running on FPGA with OS and firmware running inside Virtual Platform. Debug failures using in-system debug.

Santa Clara, California, US

Perform Firmware Integration activities for IP RTL models implemented in FPGAs which interface with reference storage and sensor devices using industry standard protocols. Provide qualification content that runs in simulation, emulation, FPGA, and Silicon targets. Debug failures to root cause and provide feedback to use case requirements and test plans.

Santa Clara, California, US

Pre-Silicon validation of Intel® IA-32 ISA-based soft IPs in Intel’s next-generation Atom SOC product. Through use of Simulation and Emulation platforms, successfully verified integration of IP into fabrics and interrupt connectivity using Linux and small, self-checking targeted tests. Developed processes to convert binary firmware images into text files.

Santa Clara, California, US

Performed Pre- and Post-Silicon validation of an embedded validation network that provides real-time debug and coverage visibility into key internal system state of the Intel® Core™ 4000-series desktop and mobile SOCs. Extended a C# programming API with a derivative class that added custom programming and user interaction controls used by validation.

Santa Clara, California, US

Delivered debug configuration software tools for Post-Silicon validation of the Intel® Core™ i7 Desktop and single-socket Server products. Debugged failures on the Core™ i7 SOC’s PCIe 2.0 and DMI interconnects using serial analyzers, JTAG run control, and proprietary internal observation and debug tools.

Santa Clara, California, US

Enabled embedded test environments to interface via chipset I2C and SMBus host controllers with custom validation hardware designed around microcontrollers, ASICs, and FPGAs. Debugged failures using protocol analyzers, processor and chipset JTAG, and simple test executables designed to reproduce failures quickly for easier analysis.

US

Worked on PHP and MySQL backend features for SourceForge.Net. Worked with fellow Professional Services Engineers to customize individual SourceForge system installations at customer sites to add additional features or user interface changes.

Santa Clara, California, US

Helped maintain a PERL-based automation system that first built a suite of executables written in Visual C then ran a nightly regression to check for newly introduced failures. The automation system produced HTML-based reports for developers to check for newly introduced failures.